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REJ09B0326-0600
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8
H8/3644 Group, H8/3644R Group H8/3644 F-ZTATTM, H8/3643 F-ZTATTM, H8/3642A F-ZTATTM
Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Series
H8/3644 HD6473644 HD6433644 HD64F3644 HD6433643 HD64F3643 HD6433642 HD64F3642A HD6433641 HD6433640 H8/3644R HD6473644R HD6433644R HD6433643R HD6433642R HD6433641R HD6433640R
H8/3643 H8/3642 H8/3641 H8/3640
H8/3643R H8/3642R H8/3641R H8/3640R
Rev. 6.00 Revision Date: Sep 12, 2006
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
Rev. 6.00 Sep 12, 2006 page ii of xx
General Precautions on Handling of Product
1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product's state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system's operation is not guaranteed if they are accessed.
Rev. 6.00 Sep 12, 2006 page iii of xx
Rev. 6.00 Sep 12, 2006 page iv of xx
Preface
The H8/300L Series of single-chip microcomputers has the high-speed H8/300L CPU at its core, with many necessary peripheral functions on-chip. The H8/300L CPU instruction set is compatible with the H8/300 CPU. The H8/3644 Group has a system-on-a-chip architecture that includes such peripheral functions as a D/A converter, five timers, a 14-bit PWM, a two-channel serial communication interface, and an A/D converter. This makes it ideal for use in advanced control systems. This manual describes the hardware of the H8/3644 Group. For details on the H8/3644 Group instruction set, refer to the H8/300L Series Programming Manual.
Rev. 6.00 Sep 12, 2006 page v of xx
Rev. 6.00 Sep 12, 2006 page vi of xx
Main Revisions in This Edition
Item All Page -- Revision (See Manual for Details) * Notification of change in company name amended (Before) Hitachi, Ltd. (After) Renesas Technology Corp. * Product naming convention amended (Before) H8/3644 Series (After) H8/3644 Group (Before) H8/3644R Series (After) H8/3644R Group 3.3.2 Interrupt Control 64 Registers Interrupt Edge Select Register 2 (IEGR2) Description amended
IEGR2 is an 8-bit read/write register, used to designate whether pins INT7 to INT0, and TMIB are set to rising edge sensing or falling edge sensing. Upon reset, IEGR2 is initialized to H'00. Bit 7INT7 Edge Select (INTEG7): Bit 7 selects the input sensing of the INT7 pin.
Bit 7: INTEG7 0 1 Description Falling edge of INT7 pin input is detected Rising edge of INT7 pin input is detected (initial value)
6.2.2
Memory Map
102, 103 Description of socket adapter deleted
Table 6.2 Socket Adapter Figure 6.2 Socket Adapter Pin Correspondence (ZTAT) 6.8.2 Memory Map 149, 151 Description of socket adapter deleted Table 6.14 Socket Adapter Product Codes Figure 6.19 Socket Adapter Pin Correspondence (F-ZTAT) 6.9 Flash Memory Programming and Erasing Precautions Table 6.18 Flash Memory AC Characteristics 8.4.2 Register Configuration and Description Port Mode Register 7 (PMR7) 182 Bit table amended
Bit Initial value Read/Write 7 1 6 1 5 1 4 1 3 1 2 TXD 0 R/W 0 1 0 POF1 0 R/W
165
Table amended
Item Flash memory read setup time*
4
Symbol tFRS
Min 50 100
Typ
Max
Unit s
Test Conditions VCC 4.5 V VCC < 4.5 V
Rev. 6.00 Sep 12, 2006 page vii of xx
Item 10.2.2 Register Descriptions Serial Control/Status Register 1 (SCSR1) 10.3.1 Overview Figure 10.6 SCI3 Block Diagram
Page 281
Revision (See Manual for Details) Description amended SCSR1 is an 8-bit register indicating operation status and error status.
291
Figure amended
SCK3 External clock Internal clock (/64, /16, /4, ) Baud rate generator
BRC Clock
BRR
Transmit/receive control circuit
SCR3 SSR
TXD
TSR
TDR
RXD
RSR
RDR Interrupt request (TEI, TXI, RXI, ERI)
10.3.7 Interrupts Table 10.16 SCI3 Interrupt Requests
336
Table amended
Vector Address H'002A
Rev. 6.00 Sep 12, 2006 page viii of xx
Internal data bus
SMR
Item 13.2.4 DC Characteristics (HD6433644, HD6433643, HD6433642, HD6433641, HD6433640) Table 13.6 DC Characteristics
Page 374
Revision (See Manual for Details) Table amended
Item Applicable Symbol Pins VCC Values Min Typ 10 Max 15 Unit mA Test Condition Notes Active (highspeed) mode VCC = 5 V, fOSC = 10 MHz VCC = 2.5 V, fOSC = 10 MHz mA 1, 2
Active IOPE1 mode current dissipation
5
1, 2 Reference value
IOPE2
VCC
2
3
Active (medium- 1, 2 speed) mode VCC = 5 V, fOSC = 10 MHz VCC = 2.5 V, fOSC = 10 MHz 1, 2 Reference value 1, 2
1
Sleep ISLEEP1 mode current dissipation
VCC
5
7
mA
Sleep (highspeed) mode VCC = 5 V, fOSC = 10 MHz VCC = 2.5 V, fOSC = 10 MHz
2
1, 2 Reference value
ISLEEP2
VCC
2
3
mA
Sleep (medium- 1, 2 speed) mode VCC = 5 V, fOSC = 10 MHz VCC = 2.5 V, fOSC = 10 MHz 1, 2 Reference value
1
13.2.5 AC Characteristics (HD6433644, HD6433643, HD6433642, HD6433641, HD6433640) Table 13.9 Serial Interface (SCI3) Timing 13.3.5 AC Characteristics (HD6433644R, HD6433643R, HD6433642R, HD6433641R, HD6433640R) Table 13.18 Serial Interface (SCI3) Timing
380
Table amended VCC = 2.5 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = 0.0 V, Ta = -20C to +75C, unless otherwise specified.
404
Table amended VCC = 2.5 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = 0.0 V, Ta = -20C to +75C, unless otherwise specified.
Rev. 6.00 Sep 12, 2006 page ix of xx
Item A.1 Instructions Table A.1 Instruction Set
Page 427
Revision (See Manual for Details) Table amended
Addressing Mode/ Instruction Length (Bytes) Condition Code
Operand Size
#xx: 8/16 Rn @Rn
Mnemonic
Operation
I
HNZVC
PUSH Rs ADD.B #xx:8, Rd
W SP-2 SP Rs16 @SP B Rd8+#xx:8 Rd8 2
2
----

0--6 2
--
B.2 Functions IEGR2--Interrupt edge select register 2
485
Bit table amended
INT7 edge select 0 Falling edge of INT7 pin input is detected 1 Rising edge of INT7 pin input is detected
Rev. 6.00 Sep 12, 2006 page x of xx

No. of States
@(d:16, Rn) @-Rn/@Rn+ @aa: 8/16 @(d:8, PC)
@@aa Implied
Contents
Section 1 Overview.............................................................................................................
1.1 1.2 1.3 Overview........................................................................................................................... Internal Block Diagram..................................................................................................... Pin Arrangement and Functions ........................................................................................ 1.3.1 Pin Arrangement .................................................................................................. 1.3.2 Pin Functions ....................................................................................................... 1 1 6 7 7 10
Section 2 CPU ...................................................................................................................... 15
2.1 Overview........................................................................................................................... 2.1.1 Features................................................................................................................ 2.1.2 Address Space...................................................................................................... 2.1.3 Register Configuration ......................................................................................... Register Descriptions ........................................................................................................ 2.2.1 General Registers ................................................................................................. 2.2.2 Control Registers.................................................................................................. 2.2.3 Initial Register Values.......................................................................................... Data Formats ..................................................................................................................... 2.3.1 Data Formats in General Registers....................................................................... 2.3.2 Memory Data Formats ......................................................................................... Addressing Modes............................................................................................................. 2.4.1 Addressing Modes................................................................................................ 2.4.2 Effective Address Calculation.............................................................................. Instruction Set ................................................................................................................... 2.5.1 Data Transfer Instructions.................................................................................... 2.5.2 Arithmetic Operations.......................................................................................... 2.5.3 Logic Operations.................................................................................................. 2.5.4 Shift Operations ................................................................................................... 2.5.5 Bit Manipulations................................................................................................. 2.5.6 Branching Instructions ......................................................................................... 2.5.7 System Control Instructions ................................................................................. 2.5.8 Block Data Transfer Instruction........................................................................... Basic Operational Timing ................................................................................................. 2.6.1 Access to On-Chip Memory (RAM, ROM) ......................................................... 2.6.2 Access to On-Chip Peripheral Modules ............................................................... CPU States ........................................................................................................................ 2.7.1 Overview.............................................................................................................. 2.7.2 Program Execution State...................................................................................... 2.7.3 Program Halt State ............................................................................................... 15 15 16 16 18 18 18 20 20 21 22 23 23 25 29 31 33 34 34 36 40 42 43 44 44 45 46 46 48 48
2.2
2.3
2.4
2.5
2.6
2.7
Rev. 6.00 Sep 12, 2006 page xi of xx
2.8 2.9
2.7.4 Exception-Handling State .................................................................................... Memory Map..................................................................................................................... Application Notes ............................................................................................................. 2.9.1 Notes on Data Access .......................................................................................... 2.9.2 Notes on Bit Manipulation ................................................................................... 2.9.3 Notes on Use of the EEPMOV Instruction ..........................................................
48 49 50 50 52 58
Section 3 Exception Handling ......................................................................................... 59
3.1 3.2 Overview........................................................................................................................... Reset 59 3.2.1 Overview.............................................................................................................. 3.2.2 Reset Sequence .................................................................................................... 3.2.3 Interrupt Immediately after Reset......................................................................... Interrupts ........................................................................................................................... 3.3.1 Overview.............................................................................................................. 3.3.2 Interrupt Control Registers................................................................................... 3.3.3 External Interrupts................................................................................................ 3.3.4 Internal Interrupts................................................................................................. 3.3.5 Interrupt Operations ............................................................................................. 3.3.6 Interrupt Response Time ...................................................................................... Application Notes ............................................................................................................. 3.4.1 Notes on Stack Area Use...................................................................................... 3.4.2 Notes on Rewriting Port Mode Registers............................................................. 59 59 59 61 61 61 63 71 72 72 77 78 78 79
3.3
3.4
Section 4 Clock Pulse Generators................................................................................... 81
4.1 Overview........................................................................................................................... 4.1.1 Block Diagram ..................................................................................................... 4.1.2 System Clock and Subclock ................................................................................. System Clock Generator.................................................................................................... Subclock Generator........................................................................................................... Prescalers .......................................................................................................................... Note on Oscillators............................................................................................................ 81 81 81 82 84 85 86
4.2 4.3 4.4 4.5
Section 5 Power-Down Modes ........................................................................................ 87
5.1 5.2 Overview........................................................................................................................... 5.1.1 System Control Registers ..................................................................................... Sleep Mode ....................................................................................................................... 5.2.1 Transition to Sleep Mode..................................................................................... 5.2.2 Clearing Sleep Mode............................................................................................ 5.2.3 Clock Frequency in Sleep (Medium-Speed) Mode .............................................. Standby Mode ................................................................................................................... 87 90 94 94 94 95 95
5.3
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5.4
5.5
5.6
5.7
5.8
5.3.1 Transition to Standby Mode................................................................................. 5.3.2 Clearing Standby Mode........................................................................................ 5.3.3 Oscillator Settling Time after Standby Mode Is Cleared ..................................... Watch Mode...................................................................................................................... 5.4.1 Transition to Watch Mode ................................................................................... 5.4.2 Clearing Watch Mode .......................................................................................... 5.4.3 Oscillator Settling Time after Watch Mode Is Cleared ........................................ Subsleep Mode.................................................................................................................. 5.5.1 Transition to Subsleep Mode ............................................................................... 5.5.2 Clearing Subsleep Mode ...................................................................................... Subactive Mode................................................................................................................. 5.6.1 Transition to Subactive Mode .............................................................................. 5.6.2 Clearing Subactive Mode..................................................................................... 5.6.3 Operating Frequency in Subactive Mode ............................................................. Active (Medium-Speed) Mode.......................................................................................... 5.7.1 Transition to Active (Medium-Speed) Mode ....................................................... 5.7.2 Clearing Active (Medium-Speed) Mode .............................................................. 5.7.3 Operating Frequency in Active (Medium-Speed) Mode ...................................... Direct Transfer ..................................................................................................................
95 95 96 96 96 97 97 97 97 98 98 98 98 99 99 99 99 99 100
Section 6 ROM..................................................................................................................... 103
6.1 6.2 Overview........................................................................................................................... 6.1.1 Block Diagram ..................................................................................................... PROM Mode..................................................................................................................... 6.2.1 Setting to PROM Mode........................................................................................ 6.2.2 Memory Map ....................................................................................................... Programming..................................................................................................................... 6.3.1 Writing and Verifying .......................................................................................... 6.3.2 Programming Precautions .................................................................................... 6.3.3 Reliability of Programmed Data........................................................................... Flash Memory Overview................................................................................................... 6.4.1 Principle of Flash Memory Operation.................................................................. 6.4.2 Mode Pin Settings and ROM Space..................................................................... 6.4.3 Features................................................................................................................ 6.4.4 Block Diagram ..................................................................................................... 6.4.5 Pin Configuration................................................................................................. 6.4.6 Register Configuration ......................................................................................... Flash Memory Register Descriptions ................................................................................ 6.5.1 Flash Memory Control Register (FLMCR) .......................................................... 6.5.2 Erase Block Register 1 (EBR1) ........................................................................... 6.5.3 Erase Block Register 2 (EBR2) ........................................................................... 103 103 104 104 104 105 106 109 110 111 111 112 112 113 114 114 115 115 117 118
6.3
6.4
6.5
Rev. 6.00 Sep 12, 2006 page xiii of xx
6.6
6.7
6.8
6.9
On-Board Programming Modes ........................................................................................ 6.6.1 Boot Mode ........................................................................................................... 6.6.2 User Program Mode............................................................................................. Programming and Erasing Flash Memory......................................................................... 6.7.1 Program Mode ..................................................................................................... 6.7.2 Program-Verify Mode.......................................................................................... 6.7.3 Programming Flowchart and Sample Program..................................................... 6.7.4 Erase Mode .......................................................................................................... 6.7.5 Erase-Verify Mode............................................................................................... 6.7.6 Erase Flowcharts and Sample Programs .............................................................. 6.7.7 Prewrite-Verify Mode .......................................................................................... 6.7.8 Protect Modes ...................................................................................................... 6.7.9 Interrupt Handling during Flash Memory Programming/Erasing......................... Flash Memory PROM Mode (H8/3644F, H8/3643F, and H8/3642AF) ........................... 6.8.1 PROM Mode Setting............................................................................................ 6.8.2 Memory Map ....................................................................................................... 6.8.3 Operation in PROM Mode................................................................................... Flash Memory Programming and Erasing Precautions .....................................................
120 120 125 127 127 128 129 132 132 133 147 148 149 150 150 150 151 160
Section 7 RAM..................................................................................................................... 167
7.1 Overview........................................................................................................................... 167 7.1.1 Block Diagram ..................................................................................................... 167
Section 8 I/O Ports .............................................................................................................. 169
8.1 8.2 Overview........................................................................................................................... Port 1................................................................................................................................. 8.2.1 Overview.............................................................................................................. 8.2.2 Register Configuration and Description............................................................... 8.2.3 Pin Functions ....................................................................................................... 8.2.4 Pin States.............................................................................................................. 8.2.5 MOS Input Pull-Up.............................................................................................. Port 2................................................................................................................................. 8.3.1 Overview.............................................................................................................. 8.3.2 Register Configuration and Description............................................................... 8.3.3 Pin Functions ....................................................................................................... 8.3.4 Pin States.............................................................................................................. Port 3................................................................................................................................. 8.4.1 Overview.............................................................................................................. 8.4.2 Register Configuration and Description............................................................... 8.4.3 Pin Functions ....................................................................................................... 8.4.4 Pin States.............................................................................................................. 169 171 171 171 175 176 176 177 177 177 179 179 180 180 180 184 185
8.3
8.4
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8.4.5 MOS Input Pull-Up.............................................................................................. Port 5................................................................................................................................. 8.5.1 Overview.............................................................................................................. 8.5.2 Register Configuration and Description............................................................... 8.5.3 Pin Functions ....................................................................................................... 8.5.4 Pin States.............................................................................................................. 8.5.5 MOS Input Pull-Up.............................................................................................. 8.6 Port 6................................................................................................................................. 8.6.1 Overview.............................................................................................................. 8.6.2 Register Configuration and Description............................................................... 8.6.3 Pin Functions ....................................................................................................... 8.6.4 Pin States.............................................................................................................. 8.7 Port 7................................................................................................................................. 8.7.1 Overview.............................................................................................................. 8.7.2 Register Configuration and Description............................................................... 8.7.3 Pin Functions ....................................................................................................... 8.7.4 Pin States.............................................................................................................. 8.8 Port 8................................................................................................................................. 8.8.1 Overview.............................................................................................................. 8.8.2 Register Configuration and Description............................................................... 8.8.3 Pin Functions ....................................................................................................... 8.8.4 Pin States.............................................................................................................. 8.9 Port 9................................................................................................................................. 8.9.1 Overview.............................................................................................................. 8.9.2 Register Configuration and Description............................................................... 8.9.3 Pin Functions ....................................................................................................... 8.9.4 Pin States.............................................................................................................. 8.10 Port B ................................................................................................................................ 8.10.1 Overview.............................................................................................................. 8.10.2 Register Configuration and Description............................................................... 8.10.3 Pin Functions ....................................................................................................... 8.10.4 Pin States.............................................................................................................. 8.5
185 186 186 186 188 189 189 190 190 190 191 192 192 192 192 194 195 195 195 196 197 198 199 199 199 200 201 201 201 201 202 202
Section 9 Timers .................................................................................................................. 203
9.1 9.2 Overview........................................................................................................................... Timer A............................................................................................................................. 9.2.1 Overview.............................................................................................................. 9.2.2 Register Descriptions ........................................................................................... 9.2.3 Timer Operation................................................................................................... 9.2.4 Timer A Operation States..................................................................................... Timer B1 ........................................................................................................................... 203 204 204 206 208 209 209
9.3
Rev. 6.00 Sep 12, 2006 page xv of xx
9.4
9.5
9.6
9.3.1 Overview.............................................................................................................. 9.3.2 Register Descriptions ........................................................................................... 9.3.3 Timer Operation................................................................................................... 9.3.4 Timer B1 Operation States................................................................................... Timer V............................................................................................................................. 9.4.1 Overview.............................................................................................................. 9.4.2 Register Descriptions ........................................................................................... 9.4.3 Timer Operation................................................................................................... 9.4.4 Timer V Operation Modes ................................................................................... 9.4.5 Interrupt Sources.................................................................................................. 9.4.6 Application Examples .......................................................................................... 9.4.7 Application Notes ................................................................................................ Timer X............................................................................................................................. 9.5.1 Overview.............................................................................................................. 9.5.2 Register Descriptions ........................................................................................... 9.5.3 CPU Interface....................................................................................................... 9.5.4 Timer Operation................................................................................................... 9.5.5 Timer X Operation Modes ................................................................................... 9.5.6 Interrupt Sources.................................................................................................. 9.5.7 Timer X Application Example ............................................................................. 9.5.8 Application Notes ................................................................................................ Watchdog Timer ............................................................................................................... 9.6.1 Overview.............................................................................................................. 9.6.2 Register Descriptions ........................................................................................... 9.6.3 Timer Operation................................................................................................... 9.6.4 Watchdog Timer Operation States .......................................................................
209 211 213 214 215 215 218 224 229 229 229 232 238 238 242 253 256 263 263 264 265 270 270 271 274 275
Section 10 Serial Communication Interface ................................................................ 277
10.1 Overview........................................................................................................................... 277 10.2 SCI1 ................................................................................................................................. 277 10.2.1 Overview.............................................................................................................. 277 10.2.2 Register Descriptions ........................................................................................... 279 10.2.3 Operation in Synchronous Mode.......................................................................... 284 10.2.4 Operation in SSB Mode ....................................................................................... 287 10.2.5 Interrupts.............................................................................................................. 289 10.3 SCI3 ................................................................................................................................. 289 10.3.1 Overview.............................................................................................................. 289 10.3.2 Register Descriptions ........................................................................................... 292 10.3.3 Operation ............................................................................................................. 309 10.3.4 Operation in Asynchronous Mode ....................................................................... 313 10.3.5 Operation in Synchronous Mode.......................................................................... 322
Rev. 6.00 Sep 12, 2006 page xvi of xx
10.3.6 Multiprocessor Communication Function ............................................................ 329 10.3.7 Interrupts.............................................................................................................. 336 10.3.8 Application Notes ................................................................................................ 337
Section 11 14-Bit PWM..................................................................................................... 341
11.1 Overview........................................................................................................................... 11.1.1 Features................................................................................................................ 11.1.2 Block Diagram ..................................................................................................... 11.1.3 Pin Configuration................................................................................................. 11.1.4 Register Configuration ......................................................................................... 11.2 Register Descriptions ........................................................................................................ 11.2.1 PWM Control Register (PWCR).......................................................................... 11.2.2 PWM Data Registers U and L (PWDRU, PWDRL)............................................ 11.3 Operation........................................................................................................................... 341 341 341 342 342 342 342 343 344
Section 12 A/D Converter................................................................................................. 345
12.1 Overview........................................................................................................................... 12.1.1 Features................................................................................................................ 12.1.2 Block Diagram ..................................................................................................... 12.1.3 Pin Configuration................................................................................................. 12.1.4 Register Configuration ......................................................................................... 12.2 Register Descriptions ........................................................................................................ 12.2.1 A/D Result Register (ADRR)............................................................................... 12.2.2 A/D Mode Register (AMR) ................................................................................. 12.2.3 A/D Start Register (ADSR).................................................................................. 12.3 Operation........................................................................................................................... 12.3.1 A/D Conversion Operation .................................................................................. 12.3.2 Start of A/D Conversion by External Trigger Input ............................................. 12.4 Interrupts ........................................................................................................................... 12.5 Typical Use ....................................................................................................................... 12.6 Application Notes ............................................................................................................. 345 345 346 347 347 348 348 348 350 351 351 351 352 352 355
Section 13 Electrical Characteristics.............................................................................. 357
13.1 Absolute Maximum Ratings.............................................................................................. 13.2 Electrical Characteristics (ZTATTM, Mask ROM Version)............................................... 13.2.1 Power Supply Voltage and Operating Range ....................................................... 13.2.2 DC Characteristics (HD6473644) ........................................................................ 13.2.3 AC Characteristics (HD6473644) ........................................................................ 13.2.4 DC Characteristics (HD6433644, HD6433643, HD6433642, HD6433641, HD6433640) ........................................................................................................ 357 358 358 361 367 371
Rev. 6.00 Sep 12, 2006 page xvii of xx
13.3
13.4
13.5 13.6
13.2.5 AC Characteristics (HD6433644, HD6433643, HD6433642, HD6433641, HD6433640) ........................................................................................................ 376 13.2.6 A/D Converter Characteristics ............................................................................. 381 Electrical Characteristics (ZTAT and R of the Mask ROM Version) ............................... 382 13.3.1 Power Supply Voltage and Operating Range ....................................................... 382 13.3.2 DC Characteristics (HD6473644R) ..................................................................... 385 13.3.3 AC Characteristics (HD6473644R) ..................................................................... 391 13.3.4 DC Characteristics (HD6433644R, HD6433643R, HD6433642R, HD6433641R, HD6433640R)...................................................................................................... 395 13.3.5 AC Characteristics (HD6433644R, HD6433643R, HD6433642R, HD6433641R, HD6433640R) ............................................................................. 400 13.3.6 A/D Converter Characteristics ............................................................................. 405 Electrical Characteristics (F-ZTAT version) ................................................................. 406 13.4.1 Power Supply Voltage and Operating Range ....................................................... 406 13.4.2 DC Characteristics (HD64F3644, HD64F3643, HD64F3642A) ......................... 409 13.4.3 AC Characteristics (HD64F3644, HD64F3643, HD64F3642A) ......................... 415 13.4.4 A/D Converter Characteristics ............................................................................. 419 Operation Timing .............................................................................................................. 420 Output Load Circuit .......................................................................................................... 423
Appendix A CPU Instruction Set.................................................................................... 425
A.1 A.2 A.3 Instructions........................................................................................................................ 425 Operation Code Map......................................................................................................... 433 Number of Execution States.............................................................................................. 435
Appendix B Internal I/O Registers ................................................................................. 442
B.1 B.2 Addresses .......................................................................................................................... 442 Functions........................................................................................................................... 446
Appendix C I/O Port Block Diagrams........................................................................... 493
C.1 C.2 C.3 C.4 C.5 C.6 C.7 C.8 C.9 Block Diagrams of Port 1.................................................................................................. Block Diagrams of Port 2.................................................................................................. Block Diagrams of Port 3.................................................................................................. Block Diagrams of Port 5.................................................................................................. Block Diagram of Port 6 ................................................................................................... Block Diagrams of Port 7.................................................................................................. Block Diagrams of Port 8.................................................................................................. Block Diagram of Port 9 ................................................................................................... Block Diagram of Port B................................................................................................... 493 497 500 503 506 507 511 519 520
Appendix D Port States in the Different Processing States..................................... 521
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Appendix E Product Code Lineup.................................................................................. 522 Appendix F Package Dimensions ................................................................................... 524
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Section 1 Overview
Section 1 Overview
1.1 Overview
The H8/300L Series is a series of single-chip microcomputers (MCU: microcomputer unit), built around the high-speed H8/300L CPU and equipped with peripheral system functions on-chip. Within the H8/300L Series, the H8/3644 Group of microcomputers are equipped with a UART (Universal Asynchronous Receiver/Transmitter). Other on-chip peripheral functions include five timers, a 14-bit pulse width modulator (PWM), two serial communication interface channels, and an A/D converter, providing an ideal configuration as a microcomputer for embedding in highlevel control systems. In addition to the mask ROM version, the H8/3644 is also available in a ZTATTM*1 version with on-chip user-programmable PROM, and an F-ZTATTM*2 version with onchip flash memory that can be programmed on-board. Table 1 summarizes the features of the H8/3644 Group. Notes: 1. ZTAT is a trademark of Renesas Technology Corp. 2. F-ZTAT is a trademark of Renesas Technology Corp.
Rev. 6.00 Sep 12, 2006 page 1 of 526 REJ09B0326-0600
Section 1 Overview
Table 1.1
Item CPU
Features
Description High-speed H8/300L CPU * General-register architecture General registers: Sixteen 8-bit registers (can be used as eight 16-bit registers) Operating speed Max. operation speed: 5 MHz (mask ROM and ZTAT versions) 8 MHz (Applies only to F-ZTAT, R of the ZTAT, and R of the mask ROM version) Add/subtract: 0.4 s (operating at = 5 MHz) 1 0.25 s (operating at = 8 MHz)* Multiply/divide: 2.8 s (operating at = 5 MHz) 1 1.75 s (operating at = 8 MHz)* Can run on 32.768 kHz subclock * Instruction set compatible with H8/300 CPU Instruction length of 2 bytes or 4 bytes Basic arithmetic operations between registers MOV instruction for data transfer between memory and registers * Typical instructions Multiply (8 bits x 8 bits) Divide (16 bits / 8 bits) Bit accumulator Register-indirect designation of bit position
*
Interrupts
33 interrupt sources * * 12 external interrupt sources (IRQ3 to IRQ0, INT7 to INT0) 21 internal interrupt sources System clock pulse generator: 1 to 10 MHz (1 to 16 MHz* ) 1 Crystal or ceramic resonator: 2 to 10 MHz (2 to 16 MHz* ) 1 External clock input: 1 to 10 MHz (1 to 16 MHz* )
1
Clock pulse generators
Two on-chip clock pulse generators *
*
Subclock pulse generator:
32.768 kHz
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Section 1 Overview Item Power-down modes Description Seven power-down modes * * * * * * * Memory * * * * * I/O ports * * Timers * Sleep (high-speed) mode Sleep (medium-speed) mode Standby mode Watch mode Subsleep mode Subactive mode Active (medium-speed) mode H8/3644: 32-kbyte ROM, 1-kbyte RAM H8/3643: 24-kbyte ROM, 1-kbyte RAM H8/3642: 16-kbyte ROM, 512 byte RAM (1-kbyte RAM F-ZTAT version) H8/3641: 12-kbyte ROM, 512 byte RAM H8/3640: 8-kbyte ROM, 512 byte RAM 45 I/O pins 8 input pins Timer A: 8-bit timer Count-up timer with selection of eight internal clock signals divided from the 2 system clock ()* and four clock signals divided from the watch clock 2 ( w)* * Timer B1: 8-bit timer Count-up timer with selection of seven internal clock signals or event input from external pin Auto-reloading * Timer V: 8-bit timer Count-up timer with selection of six internal clock signals or event input from external pin Compare-match waveform output Externally triggerable
Large on-chip memory
53 pins
Five on-chip timers
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Section 1 Overview Item Timers Description * Timer X: 16-bit timer Count-up timer with selection of three internal clock signals or event input from external pin Output compare (2 output pins) Input capture (4 input pins) * Watchdog timer Reset signal generated by 8-bit counter overflow Serial Two on-chip serial communication interface channels communication * SCI1: synchronous serial interface interface Choice of 8-bit or 16-bit data transfer * 14-bit PWM SCI3: 8-bit synchronous/asynchronous serial interface Incorporates multiprocessor communication function Pulse-division PWM output for reduced ripple * A/D converter Can be used as a 14-bit D/A converter by connecting to an external low-pass filter. 8-channel analog input pins Conversion time: 31/ or 62/ per channel
Successive approximations using a resistance ladder * *
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Section 1 Overview Item Product lineup
Mask ROM Version HD6433644H HD6433644RH HD6433644P HD6433644RP HD6433644W HD6433644RW HD6433643H HD6433643RH HD6433643P HD6433643RP HD6433643W HD6433643RW HD6433642H HD6433642RH HD6433642P HD6433642RP HD6433642W HD6433642RW HD6433641H HD6433641RH HD6433641P HD6433641RP HD6433641W HD6433641RW HD6433640H HD6433640RH HD6433640P HD6433640RP HD6433640W HD6433640RW
Description
Product Code ZTATTM Version HD6473644H HD6473644RH HD6473644P HD6473644RP F-ZTATTM Version HD64F3644H HD64F3644P Package 64-pin QFP (FP-64A) 64-pin SDIP (DP-64S) 80-pin TQFP (TFP-80C) 64-pin QFP (FP-64A) 64-pin SDIP (DP-64S) 80-pin TQFP (TFP-80C) 64-pin QFP (FP-64A) 64-pin SDIP (DP-64S) ROM: 16 kbytes RAM: 512 kbytes RAM: 1 kbyte (F-ZTAT version) ROM: 24 kbytes RAM: 1 kbyte ROM/RAM Size ROM: 32 kbytes RAM: 1 kbyte
HD6473644W HD64F3644W HD6473644RW HD64F3643H HD64F3643P HD64F3643W HD64F3642AH HD64F3642AP
HD64F3642AW 80-pin TQFP (TFP-80C) 64-pin QFP (FP-64A) 64-pin SDIP (DP-64S) 80-pin TQFP (TFP-80C) 64-pin QFP (FP-64A) 64-pin SDIP (DP-64S) 80-pin TQFP (TFP-80C) ROM: 8 kbytes RAM: 512 bytes ROM: 12 kbytes RAM: 512 bytes
Notes: 1. Applies only to F-ZTAT, R of the ZTAT, and R of the mask ROM version. 2. As for the definition of and W , see section 4, Clock Pulse Generators.
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Section 1 Overview
1.2
Internal Block Diagram
Figure 1.1 shows a block diagram of the H8/3644 Group.
OSC1 OSC2
System clock generator
Subclock generator
VSS VCC RES IRQ0 TEST
CPU H8/300L
X1 X2
Data bus (upper)
Address bus
Data bus (lower)
P10/TMOW P14/PWM P15/IRQ1 P16/IRQ2 P17/IRQ3/TRGV
Port 1
ROM
RAM
P87 P86/FTID P85/FTIC P84/FTIB P83/FTIA P82/FTOB P81/FTOA P80/FTCI
Port 8 Port 7
P20/SCK3 P21/RXD P22/TXD
Timer A
SCI1
P77 P76/TMOV P75/TMCIV P74/TMRIV P73
Port 2
Timer B1 P30/SCK1 P31/SI1 P32/SO1
SCI3
Port 3
Timer V
P90/FVPP* P91 P92 P93 P94
Port 9
Watchdog timer
14-bit PWM
Port 6
Timer X
P67 P66 P65 P64 P63 P62 P61 P60
CMOS largecurrent port IOL= 10 mA @VOL= 1V
A/D converter
P57/INT7 P56/INT6/TMIB P55/INT5/ADTRG P54/INT4 P53/INT3 P52/INT2 P51/INT1 P50/INT0
Port B
AVCC AVSS
Note: * There is no P90 function in the flash memory version.
Figure 1.1 Block Diagram
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PB0/AN0 PB1/AN1 PB2/AN2 PB3/AN3 PB4/AN4 PB5/AN5 PB6/AN6 PB7/AN7
Port 5
Section 1 Overview
1.3
1.3.1
Pin Arrangement and Functions
Pin Arrangement
The H8/3644 Group pin arrangement is shown in figures 1.2 (FP-64A), 1.3 (DP-64S), and 1.4 (TFP-80C).
P75/TMCIV
P76/TMOV
P86/FTID
P21/RXD
P74/TMRIV
P82/FTOB
P81/FTOA
P20/SCK3
P85/FTIC
P80/FTCI
P84/FTIB
P83/FTIA
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
P22/TXD P32/SO1 P31/SI1 P30/SCK1 P10/TMOW P14/PWM P15/IRQ1 P16/IRQ2 P17/IRQ3/TRGV AVCC PB7/AN7 PB6/AN6 PB5/AN5 PB4/AN4 PB3/AN3 PB2/AN2
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
33
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VCC
P87
P77
P73
P57/INT7 P56/INT6/TMIB P55/INT5/ADTRG P54/INT4 P53/INT3 P52/INT2 P51/INT1 P50/INT0 P67 P66 P65 P64 P63 P62 P61 P60
10
11
12
13
14
15 P94
RES
P90/FVPP*
PB1/AN1
PB0/AN0
TEST
X2
X1
OSC1
OSC2
P91
P92
P93
AVSS
Note: * There is no P90 function in the flash memory version.
Figure 1.2 Pin Arrangement (FP-64A: Top View)
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IRQ0
VSS
16
1
2
3
4
5
6
7
8
9
Section 1 Overview
P17/IRQ3/TRGV AVCC PB7/AN7 PB6/AN6 PB5/AN5 PB4/AN4 PB3/AN3 PB2/AN2 PB1/AN1 PB0/AN0 AVSS TEST X2 X1 VSS OSC1 OSC2 RES P90/FVPP* P91 P92 P93 P94 IRQ0 P60 P61 P62 P63 P64 P65 P66 P67
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P16/IRQ2 P15/IRQ1 P14/PWM P10/TMOW P30/SCK1 P31/SI1 P32/SO1 P22/TXD P21/RXD P20/SCK3 P87 P86/FTID P85/FTIC P84/FTIB P83/FTIA P82/FTOB P81/FTOA P80/FTCI P77 P76/TMOV P75/TMCIV P74/TMRIV P73 VCC P57/INT7 P56/INT6/TMIB P55/INT5/ADTRG P54/INT4 P53/INT3 P52/INT2 P51/INT1 P50/INT0
Note: * There is no P90 function in the flash memory version.
Figure 1.3 Pin Arrangement (DP-64S: Top View)
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Section 1 Overview
Note: * There is no P90 function in the flash memory version.
Figure 1.4 Pin Arrangement (TFP-80C: Top View)
NC PB1/AN1 PB0/AN0 AVSS TEST X2 X1 VSS1 OSC1 OSC2 VSS2 RES P90/FVPP* P91 P92 NC P93 P94 IRQ0 NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
NC NC P22/TXD P32/SO1 P31/SI1 P30/SCK1 P10/TMOW P14/PWM P15/IRQ1 P16/IRQ2 P17/IRQ3/TRGV AVCC PB7/AN7 PB6/AN6 PB5/AN5 PB4/AN4 PB3/AN3 PB2/AN2 NC NC
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
NC P21/RXD P20/SCK3 P87 P86/FTID P85/FTIC P84/FTIB NC P83/FTIA P82/FTOB P81/FTOA P80/FTCI NC P77 P76/TMOV P75/TMCIV P74/TMRIV P73 VCC NC 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 NC NC P57/INT7 P56/INT6/TMIB P55/INT5/ADTRG P54/INT4 P53/INT3 P52/INT2 P51/INT1 P50/INT0 NC P67 P66 P65 P64 P63 P62 P61 P60 NC
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Section 1 Overview
1.3.2
Pin Functions
Table 1.2 outlines the pin functions of the H8/3644 Group. Table 1.2 Pin Functions
Pin No. Type Symbol FP-64A 33 DP-64S 41 TFP-80C I/O 42 Input Name and Functions Power supply: All VCC pins should be connected to the user system VCC. Ground: All VSS pins should be connected to the user system GND. Analog power supply: This is the power supply pin for the A/D converter. When the A/D converter is not used, connect this pin to the user system VCC. Analog ground: This is the A/D converter ground pin. It should be connected to the user system GND. System clock: These pins connect to a crystal or ceramic resonator, or can be used to input an external clock. See section 4, Clock Pulse Generators, for a typical connection diagram. Subclock: These pins connect to a 32.768-kHz crystal resonator. See section 4, Clock Pulse Generators, for a typical connection diagram. Reset: When this pin is driven low, the chip is reset Test: This is a test pin, not for use in application systems. It should be connected to VSS. Power VCC source pins VSS
7
15
8, 11
Input
AVCC
58
2
72
Input
AVSS
3
11
4
Input
Clock pins
OSC1
8
16
9
Input
OSC2
9
17
10
Output
X1 X2
6 5
14 13
7 6
Input Output
System control
RES TEST
10 4
18 12
12 5
Input Input
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Section 1 Overview Pin No. Type Interrupt pins Symbol IRQ0 IRQ1 IRQ2 IRQ3 INT7 to INT0 FP-64A 16 55 56 57 32 to 25 DP-64S 24 63 64 1 40 to 33 TFP-80C I/O 19 69 70 71 38 to 31 Input Name and Functions IRQ interrupt request 0 to 3: These are input pins for edgesensitive external interrupts, with a selection of rising or falling edge INT interrupt request 0 to 7: These are input pins for edgesensitive external interrupts, with a selection of rising or falling edge Clock output: This is an output pin for waveforms generated by the timer A output circuit Timer B1 event counter input: This is an event input pin for input to the timer B1 counter Timer V output: This is an output pin for waveforms generated by the timer V output compare function Timer V event input: This is an event input pin for input to the timer V counter Timer V counter reset: This is a counter reset input pin for timer V Timer V counter trigger input: This is a trigger input pin for the timer V counter and realtime output port Timer X clock input: This is an external clock input pin for input to the timer X counter Timer X output compare A output: This is an output pin for timer X output compare A Timer X output compare B output: This is an output pin for timer X output compare B
Input
Timer pins
TMOW
53
61
67
Output
TMIB
31
39
37
Input
TMOV
37
45
46
Output
TMCIV
36
44
45
Input
TMRIV TRGV
35 57
43 1
44 71
Input Input
FTCI
39
47
49
Input
FTOA
40
48
50
Output
FTOB
41
49
51
Output
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Section 1 Overview Pin No. Type Timer pins Symbol FTIA FP-64A 42 DP-64S 50 TFP-80C I/O 52 Input Name and Functions Timer X input capture A input: This is an input pin for timer X input capture A Timer X input capture B input: This is an input pin for timer X input capture B Timer X input capture C input: This is an input pin for timer X input capture C Timer X input capture D input: This is an input pin for timer X input capture D 14-bit PWM output: This is an output pin for waveforms generated by the 14-bit PWM Port B: This is an 8-bit input port Port 1: This is a 5-bit I/O port. Input or output can be designated for each bit by means of port control register 1 (PCR1) Port 2: This is a 3-bit I/O port. Input or output can be designated for each bit by means of port control register 2 (PCR2) Port 3: This is a 3-bit I/O port. Input or output can be designated for each bit by means of port control register 3 (PCR3) Port 5: This is an 8-bit I/O port. Input or output can be designated for each bit by means of port control register 5 (PCR5) Port 6: This is an 8-bit I/O port. Input or output can be designated for each bit by means of port control register 6 (PCR6)
FTIB
43
51
54
Input
FTIC
44
52
55
Input
FTID
45
53
56
Input
14-bit PWM pin I/O ports
PWM
54
62
68
Output
PB7 to PB0 P17 to P14, P10 P22 to P20
59 to 64, 3 to 10 1, 2 57 to 53 1, 64 to 61
73 to 78 2, 3 71 to 67
Input I/O
49 to 47
57 to 55
63, 59 58
I/O
P32 to P30
50 to 52
58 to 60
64 to 66
I/O
P57 to P50
32 to 25
40 to 33
38 to 31
I/O
P67 to P60
24 to 17
32 to 25
29 to 22
I/O
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Section 1 Overview Pin No. Type I/O ports Symbol P77 to P73 FP-64A 38 to 34 DP-64S 46 to 42 TFP-80C I/O 47 to 43 I/O Name and Functions Port 7: This is a 5-bit I/O port. Input or output can be designated for each bit by means of port control register 7 (PCR7) Port 8: This is an 8-bit I/O port. Input or output can be designated for each bit by means of port control register 8 (PCR8) Port 9: This is a 5-bit I/O port. Input or output can be designated for each bit by means of port control register 9 (PCR9) Note: There is no P90 function in the flash memory version since P90 is used as the FVPP pin. Serial com- SI1 munication interface SO1 (SCI) SCK1 RXD TXD SCK3 A/D converter AN7 to AN0 ADTRG 51 50 52 48 49 47 59 58 60 56 57 55 65 64 66 59 63 58 73 to 78 2, 3 36 Input Output I/O Input Output I/O Input SCI1 receive data input: This is the SCI1 data input pin SCI1 transmit data output: This is the SCI1 data output pin SCI1 clock I/O: This is the SCI1 clock I/O pin SCI3 receive data input: This is the SCI3 data input pin SCI3 transmit data output: This is the SCI3 data output pin SCI3 clock I/O: This is the SCI3 clock I/O pin Analog input channels 11 to 0: These are analog data input channels to the A/D converter A/D converter trigger input: This is the external trigger input pin to the A/D converter
P87 to P80
46 to 39
54 to 47
57 to 54, I/O 52 to 49
P94 to P90
15 to 11
23 to 19
18, 17 15 to 13
I/O
59 to 64, 3 to 10 1, 2 30 38
Input
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Section 1 Overview Pin No. Type Flash memory Symbol FVPP FP-64A 11 DP-64S 19 TFP-80C I/O 13 Input Name and Functions On-board-programmable flash memory power supply: Connected to the flash memory programming power supply (+12 V). When the flash memory is not being programmed, connect to the user system VCC. In versions other than the on-chip flash memory version, this pin is P90 Non-connected pins: These pins must be left unconnected
Other
NC
1, 16, 20, 21, 30, 39, 40, 41, 48, 53, 60 to 62, 79, 80
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Section 2 CPU
Section 2 CPU
2.1 Overview
The H8/300L CPU has sixteen 8-bit general registers, which can also be paired as eight 16-bit registers. Its concise instruction set is designed for high-speed operation. 2.1.1 Features
Features of the H8/300L CPU are listed below. * General-register architecture Sixteen 8-bit general registers, also usable as eight 16-bit general registers * Instruction set with 55 basic instructions, including: Multiply and divide instructions Powerful bit-manipulation instructions * Eight addressing modes Register direct Register indirect Register indirect with displacement Register indirect with post-increment or pre-decrement Absolute address Immediate Program-counter relative Memory indirect * 64-kbyte address space * High-speed operation All frequently used instructions are executed in two to four states High-speed arithmetic and logic operations 8- or 16-bit register-register add or subtract: 0.4 s (operating at = 5 MHz) 0.25 s (operating at = 8 MHz)* 8 x 8-bit multiply: 2.8 s (operating at = 5 MHz) 1.75 s (operating at = 8 MHz)* 16 / 8-bit divide: 2.8 s (operating at = 5 MHz) 1.75 s (operating at = 8 MHz)* Note: * Applies only to F-ZTAT, R of the ZTAT, and R of the mask ROM version.
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Section 2 CPU
* Low-power operation modes SLEEP instruction for transfer to low-power operation 2.1.2 Address Space
The H8/300L CPU supports an address space of up to 64 kbytes for storing program code and data. See section 2.8, Memory Map, for details of the memory map. 2.1.3 Register Configuration
Figure 2.1 shows the register structure of the H8/300L CPU. There are two groups of registers: the general registers and control registers.
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Section 2 CPU
General registers (Rn) 7 R0H R1H R2H R3H R4H R5H R6H R7H (SP) 07 R0L R1L R2L R3L R4L R5L R6L R7L SP: Stack pointer 0
Control registers (CR) 15 PC 76543210 I UHUNZVC 0 PC: Program counter CCR: Condition code register Carry flag Overflow flag Zero flag Negative flag Half-carry flag Interrupt mask bit User bit User bit
CCR
Figure 2.1 CPU Registers
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Section 2 CPU
2.2
2.2.1
Register Descriptions
General Registers
All the general registers can be used as both data registers and address registers. When used as data registers, they can be accessed as 16-bit registers (R0 to R7), or the high bytes (R0H to R7H) and low bytes (R0L to R7L) can be accessed separately as 8-bit registers. When used as address registers, the general registers are accessed as 16-bit registers (R0 to R7). R7 also functions as the stack pointer (SP), used implicitly by hardware in exception processing and subroutine calls. When it functions as the stack pointer, as indicated in figure 2.2, SP (R7) points to the top of the stack.
Lower address side [H'0000] Unused area SP (R7) Stack area
Upper address side [H'FFFF]
Figure 2.2 Stack Pointer 2.2.2 Control Registers
The CPU control registers include a 16-bit program counter (PC) and an 8-bit condition code register (CCR). Program Counter (PC): This 16-bit register indicates the address of the next instruction the CPU will execute. All instructions are fetched 16 bits (1 word) at a time, so the least significant bit of the PC is ignored (always regarded as 0).
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Section 2 CPU
Condition Code Register (CCR): This 8-bit register contains internal status information, including the interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. These bits can be read and written by software (using the LDC, STC, ANDC, ORC, and XORC instructions). The N, Z, V, and C flags are used as branching conditions for conditional branching (Bcc) instructions. Bit 7Interrupt Mask Bit (I): When this bit is set to 1, interrupts are masked. This bit is set to 1 automatically at the start of exception handling. The interrupt mask bit may be read and written by software. For further details, see section 3.3, Interrupts. Bit 6User Bit (U): Can be used freely by the user. Bit 5Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and is cleared to 0 otherwise. The H flag is used implicitly by the DAA and DAS instructions. When the ADD.W, SUB.W, or CMP.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and is cleared to 0 otherwise. Bit 4User Bit (U): Can be used freely by the user. Bit 3VNegative Flag (N): Indicates the most significant bit (sign bit) of the result of an instruction. Bit 2Zero Flag (Z): Set to 1 to indicate a zero result, and cleared to 0 to indicate a non-zero result. Bit 1Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. Bit 0Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: * Add instructions, to indicate a carry * Subtract instructions, to indicate a borrow * Shift/rotate carry The carry flag is also used as a bit accumulator by bit manipulation instructions. Some instructions leave some or all of the flag bits unchanged.
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Section 2 CPU
Refer to the H8/300L Series Programming Manual for the action of each instruction on the flag bits. 2.2.3 Initial Register Values
In reset exception handling, the program counter (PC) is initialized by a vector address (H'0000) load, and the I bit in the CCR is set to 1. The other CCR bits and the general registers are not initialized. In particular, the stack pointer (R7) is not initialized. The stack pointer should be initialized by software, by the first instruction executed after a reset.
2.3
Data Formats
The H8/300L CPU can process 1-bit data, 4-bit (BCD) data, 8-bit (byte) data, and 16-bit (word) data. The H8/300L CPU can process 1-bit, 4-bit BCD, 8-bit (byte), and 16-bit (word) data. 1-bit data is handled by bit manipulation instructions, and is accessed by being specified as bit n (n = 0, 1, 2, ... 7) in the operand data (byte). Byte data is handled by all arithmetic and logic instructions except ADDS and SUBS. Word data is handled by the MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (b bits x 8 bits), and DIVXU (16 bits / 8 bits) instructions. With the DAA and DAS decimal adjustment instructions, byte data is handled as two 4-bit BCD data units.
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Section 2 CPU
2.3.1
Data Formats in General Registers
Data of all the sizes above can be stored in general registers as shown in figure 2.3.
Data Type Register No.
7
Data Format
0
1-bit data
RnH
7
6
5
4
3
2
1
0
don't care
7
0
1-bit data
RnL
don't care
7
6
5
4
3
2
1
0
7
0 LSB
Byte data
RnH
MSB
don't care
7
0 LSB
Byte data
RnL
don't care
MSB
15
0 LSB
Word data
Rn
MSB
7
4 Upper digit
3 Lower digit
0
4-bit BCD data
RnH
don't care
7
4 Upper digit
3 Lower digit
0
4-bit BCD data
RnL
don't care
Legend: RnH: Upper byte of general register RnL: Lower byte of general register MSB: Most significant bit LSB: Least significant bit
Figure 2.3 General Register Data Formats
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Section 2 CPU
2.3.2
Memory Data Formats
Figure 2.4 indicates the data formats in memory. For access by the H8/300L CPU, word data stored in memory must always begin at an even address. When word data beginning at an odd address is accessed, the least significant bit is regarded as 0, and the word data beginning at the preceding address is accessed. The same applies to instruction codes.
Data Type Address Data Format
7
0
1-bit data Byte data
Address n Address n Even address Odd address Even address Odd address Even address Odd address
7
MSB
6
5
4
3
2
1
0
LSB
Word data
MSB
Upper 8 bits Lower 8 bits LSB
Byte data (CCR) on stack
MSB MSB
CCR CCR*
LSB LSB
Word data on stack
MSB LSB
Legend: CCR: Condition code register Note: * Ignored on return
Figure 2.4 Memory Data Formats When the stack is accessed using R7 as an address register, word access should always be performed. The CCR is stored as word data with the same value in the upper 8 bits and the lower 8 bits. On return, the lower 8 bits are ignored.
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Section 2 CPU
2.4
2.4.1
Addressing Modes
Addressing Modes
The H8/300L CPU supports the eight addressing modes listed in table 2.1. Each instruction uses a subset of these addressing modes. Table 2.1
No. 1 2 3 4 5 6 7 8
Addressing Modes
Address Modes Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect Symbol Rn @Rn @(d:16, Rn) @Rn+ @-Rn @aa:8 or @aa:16 #xx:8 or #xx:16 @(d:8, PC) @@aa:8
1. Register DirectRn: The register field of the instruction specifies an 8- or 16-bit general register containing the operand. Only the MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits x 8 bits), and DIVXU (16 bits / 8 bits) instructions have 16-bit operands. 2. Register Indirect@Rn: The register field of the instruction specifies a 16-bit general register containing the address of the operand in memory. 3. Register Indirect with Displacement@(d:16, Rn): The instruction has a second word (bytes 3 and 4) containing a displacement which is added to the contents of the specified general register to obtain the operand address in memory. This mode is used only in MOV instructions. For the MOV.W instruction, the resulting address must be even. 4. Register Indirect with Post-Increment or Pre-Decrement@Rn+ or @-Rn: Register indirect with post-increment@Rn+ The @Rn+ mode is used with MOV instructions that load registers from memory. The register field of the instruction specifies a 16-bit general register containing the address of the operand. After the operand is accessed, the register is incremented by 1 for MOV.B or 2 for MOV.W, and the result of the addition is stored in the register. For MOV.W, the original contents of the 16-bit general register must be even.
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Section 2 CPU
Register indirect with pre-decrement@-Rn The @-Rn mode is used with MOV instructions that store register contents to memory. The register field of the instruction specifies a 16-bit general register which is decremented by 1 or 2 to obtain the address of the operand in memory. The register retains the decremented value. The size of the decrement is 1 for MOV.B or 2 for MOV.W. For MOV.W, the original contents of the register must be even. 5. Absolute Address@aa:8 or @aa:16: The instruction specifies the absolute address of the operand in memory. The absolute address may be 8 bits long (@aa:8) or 16 bits long (@aa:16). The MOV.B and bit manipulation instructions can use 8-bit absolute addresses. The MOV.B, MOV.W, JMP, and JSR instructions can use 16-bit absolute addresses. For an 8-bit absolute address, the upper 8 bits are assumed to be 1 (H'FF). The address range is H'FF00 to H'FFFF (65280 to 65535). 6. Immediate#xx:8 or #xx:16: The second byte (#xx:8) or the third and fourth bytes (#xx:16) of the instruction code are used directly as the operand. Only MOV.W instructions can be used with #xx:16. The ADDS and SUBS instructions implicitly contain the value 1 or 2 as immediate data. Some bit manipulation instructions contain 3-bit immediate data in the second or fourth byte of the instruction, specifying a bit number. 7. Program-Counter Relative@(d:8, PC): This mode is used in the Bcc and BSR instructions. An 8-bit displacement in byte 2 of the instruction code is sign-extended to 16 bits and added to the program counter contents to generate a branch destination address, and the PC contents to be added are the start address of the next instruction, so that the possible branching range is -126 to +128 bytes (-63 to +64 words) from the branch instruction. The displacement should be an even number. 8. Memory Indirect@@aa:8: This mode can be used by the JMP and JSR instructions. The second byte of the instruction code specifies an 8-bit absolute address. This specifies an operand in memory, and a branch is performed with the contents of this operand as the branch address. The upper 8 bits of the absolute address are assumed to be 0 (H'00), so the address range is from H'0000 to H'00FF (0 to 255). Note that with the H8/300L Series, the lower end of the address area is also used as a vector area. See section 3.3, Interrupts, for details on the vector area. If an odd address is specified as a branch destination or as the operand address of a MOV.W instruction, the least significant bit is regarded as 0, causing word access to be performed at the address preceding the specified address. See section 2.3.2, Memory Data Formats, for further information.
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Section 2 CPU
2.4.2
Effective Address Calculation
Table 2.2 shows how effective addresses are calculated in each of the addressing modes. Arithmetic and logic instructions use register direct addressing (1). The ADD.B, ADDX, SUBX, CMP.B, AND, OR, and XOR instructions can also use immediate addressing (6). Data transfer instructions can use all addressing modes except program-counter relative (7) and memory indirect (8). Bit manipulation instructions use register direct (1), register indirect (2), or 8-bit absolute addressing (5) to specify a byte operand, and 3-bit immediate addressing (6) to specify a bit position in that byte. The BSET, BCLR, BNOT, and BTST instructions can also use register direct addressing (1) to specify the bit position.
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Table 2.2
No. 1
Effective Address Calculation
Effective Address Calculation Method Effective Address (EA)
3 0 3 0
Addressing Mode and Instruction Format
Register indirect, Rn
15 87 43 0
rm op rm rn
rn
Operand is contents of registers indicated by rm/rn
15 Contents (16 bits) of register indicated by rm 0 15 0
2
Register indirect, @Rn
15
76 43
0
op
rm
3
Register indirect with displacement, @(d:16, Rn)
15 76 43 0
15 Contents (16 bits) of register indicated by rm
0 15 0
op disp
rm
disp
4
Register indirect with post-increment, @Rn+
15 76 43 0
15 Contents (16 bits) of register indicated by rm
0
15
0
op
rm 1 or 2
Register indirect with pre-decrement, @-Rn
15 76 43 0
15 Contents (16 bits) of register indicated by rm
0 15 0
op
rm
Incremented or decremented by 1 if operand is byte size, 1 or 2 and by 2 if word size
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Section 2 CPU Addressing Mode and Instruction Format
Absolute address @aa:8
15 87 0
No. 5
Effective Address Calculation Method
Effective Address (EA)
15 87 0
H'FF
op @aa:16
15
abs
0
15
0
op abs
6
Immediate #xx:8
15 87 0
Operand is 1- or 2-byte immediate data IMM
op #xx:16
15
0
op IMM
7
Program-counter relative @(d:8, PC)
15
0
PC contents
15 0
15
87
0
Sign extension
disp
op
disp
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Section 2 CPU Addressing Mode and Instruction Format
Memory indirect, @@aa:8
15 87 0
No. 8
Effective Address Calculation Method
Effective Address (EA)
op
abs
15 87 0
H'00
abs
15 0
Memory contents (16 bits)
Legend: rm, rn: Register field op: Operation field disp: Displacement IMM: Immediate data abs: Absolute address
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Section 2 CPU
2.5
Instruction Set
The H8/300L Series can use a total of 55 instructions, which are grouped by function in table 2.3. Table 2.3
Function Data transfer Arithmetic operations Logic operations Shift Bit manipulation Branch System control Block data transfer
Instruction Set
Instructions
1 1 MOV, PUSH* , POP*
Number 1 14 4 8 14 5 8 1 Total: 55
ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS, MULXU, DIVXU, CMP, NEG AND, OR, XOR, NOT SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST 2 Bcc* , JMP, BSR, JSR, RTS RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP EEPMOV
Notes: 1. PUSH Rn is equivalent to MOV.W Rn, @-SP. POP Rn is equivalent to MOV.W @SP+, Rn. 2. Bcc is a conditional branch instruction. The same applies to machine language.
Tables 2.4 to 2.11 show the function of each instruction. The notation used is defined next.
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Notation
Rd Rs Rn (EAd), (EAs), CCR N Z V C PC SP #IMM disp + - x / ~ :3 :8 :16 ( ), < > General register (destination) General register (source) General register Destination operand Source operand Condition code register N (negative) flag of CCR Z (zero) flag of CCR V (overflow) flag of CCR C (carry) flag of CCR Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division AND logical OR logical Exclusive OR logical Move Logical negation (logical complement) 3-bit length 8-bit length 16-bit length Contents of operand indicated by effective address
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2.5.1
Data Transfer Instructions
Table 2.4 describes the data transfer instructions. Figure 2.5 shows their object code formats. Table 2.4
Instruction MOV
Data Transfer Instructions
Size* B/W Function (EAs) Rd, Rs (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. The Rn, @Rn, @(d:16, Rn), @aa:16, #xx:16, @-Rn, and @Rn+ addressing modes are available for word data. The @aa:8 addressing mode is available for byte data only. The @-R7 and @R7+ modes require a word-size specification.
POP
W
@SP+ Rn Pops a general register from the stack. Equivalent to MOV.W @SP+, Rn.
PUSH
W
Rn @-SP Pushes general register onto the stack. Equivalent to MOV.W Rn, @-SP.
Notes: * Size: Operand size B: Byte W: Word
Certain precautions are required in data access. See section 2.9.1, Notes on Data Access, for details.
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15 8 7 0
MOV RmRn
op
15 8 7
rm
rn
0
op
15 8 7
rm
rn
0
@RmRn
op disp
15 8 7
rm
rn
@(d:16, Rm)Rn
0
op
15 8 7
rm
rn
0
@Rm+Rn, or Rn @-Rm
op
15
rn
8 7
abs
0
@aa:8Rn
op abs
15 8 7
rn
@aa:16Rn
0
op
15
rn
8 7
IMM
0
#xx:8Rn
op IMM
15 8 7
rn
#xx:16Rn
0
op Legend: op: Operation field rm, rn: Register field disp: Displacement abs: Absolute address IMM: Immediate data
1
1
1
rn
PUSH, POP @SP+ Rn, or Rn @-SP
Figure 2.5 Data Transfer Instruction Codes
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Section 2 CPU
2.5.2
Arithmetic Operations
Table 2.5 describes the arithmetic instructions. Table 2.5
Instruction ADD SUB
Arithmetic Instructions
Size* B/W Function Rd Rs Rd, Rd + #IMM Rd Performs addition or subtraction on data in two general registers, or addition on immediate data and data in a general register. Immediate data cannot be subtracted from data in a general register. Word data can be added or subtracted only when both words are in general registers. B Rd Rs C Rd, Rd #IMM C Rd Performs addition or subtraction with carry on data in two general registers, or addition or subtraction with carry on immediate data and data in a general register. B W B Rd 1 Rd Increments or decrements a general register Rd 1 Rd, Rd 2 Rd Adds or subtracts 1 or 2 to or from a general register Rd decimal adjust Rd Decimal-adjusts (adjusts to packed BCD) an addition or subtraction result in a general register by referring to the CCR B Rd x Rs Rd Performs 8-bit x 8-bit unsigned multiplication on data in two general registers, providing a 16-bit result
ADDX SUBX
INC DEC ADDS SUBS DAA DAS MULXU
DIVXU
B
Rd / Rs Rd Performs 16-bit / 8-bit unsigned division on data in two general registers, providing an 8-bit quotient and 8-bit remainder
CMP
B/W
Rd - Rs, Rd - #IMM Compares data in a general register with data in another general register or with immediate data, and indicates the result in the CCR. Word data can be compared only between two general registers.
NEG
B
0 - Rd Rd Obtains the two's complement (arithmetic complement) of data in a general register
Notes: * Size: Operand size B: Byte W: Word Rev. 6.00 Sep 12, 2006 page 33 of 526 REJ09B0326-0600
Section 2 CPU
2.5.3
Logic Operations
Table 2.6 describes the four instructions that perform logic operations. Table 2.6
Instruction AND
Logic Operation Instructions
Size* B Function Rd Rs Rd, Rd #IMM Rd Performs a logical AND operation on a general register and another general register or immediate data
OR
B
Rd Rs Rd, Rd #IMM Rd Performs a logical OR operation on a general register and another general register or immediate data
XOR
B
Rd Rs Rd, Rd #IMM Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data
NOT
B
~ Rd Rd Obtains the one's complement (logical complement) of general register contents
Notes: * Size: Operand size B: Byte
2.5.4
Shift Operations
Table 2.7 describes the eight shift instructions. Table 2.7
Instruction SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR B B B
Shift Instructions
Size* B Function Rd shift Rd Performs an arithmetic shift operation on general register contents Rd shift Rd Performs a logical shift operation on general register contents Rd rotate Rd Rotates general register contents Rd rotate Rd Rotates general register contents through the C (carry) bit
Notes: * Size: Operand size B: Byte Rev. 6.00 Sep 12, 2006 page 34 of 526 REJ09B0326-0600
Section 2 CPU
Figure 2.6 shows the instruction code format of arithmetic, logic, and shift instructions.
15 8 7 0
op
15 8 7
rm
rn
0
ADD, SUB, CMP, ADDX, SUBX (Rm) ADDS, SUBS, INC, DEC, DAA, DAS, NEG, NOT
0
op
15 8 7
rn
op
15 8 7
rm
rn
0
MULXU, DIVXU
op
15
rn
8 7
IMM
0
ADD, ADDX, SUBX, CMP (#XX:8)
op
15 8 7
rm
rn
0
AND, OR, XOR (Rm)
op
15
rn
8 7
IMM
0
AND, OR, XOR (#xx:8)
op Legend: op: Operation field rm, rn: Register field IMM: Immediate data
rn
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR
Figure 2.6 Arithmetic, Logic, and Shift Instruction Codes
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Section 2 CPU
2.5.5
Bit Manipulations
Table 2.8 describes the bit-manipulation instructions. Figure 2.7 shows their object code formats. Table 2.8
Instruction BSET
Bit-Manipulation Instructions
Size* B Function 1 ( of ) Sets a specified bit in a general register or memory to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
BCLR
B
0 ( of ) Clears a specified bit in a general register or memory to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
BNOT
B
~ ( of ) ( of ) Inverts a specified bit in a general register or memory. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
BTST
B
~ ( of ) Z Tests a specified bit in a general register or memory and sets or clears the Z flag accordingly. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
BAND
B
C ( of ) C ANDs the C flag with a specified bit in a general register or memory, and stores the result in the C flag.
BIAND
B
C [~ ( of )] C ANDs the C flag with the inverse of a specified bit in a general register or memory, and stores the result in the C flag. The bit number is specified by 3-bit immediate data.
BOR
B
C ( of ) C ORs the C flag with a specified bit in a general register or memory, and stores the result in the C flag.
BIOR
B
C [~ ( of )] C ORs the C flag with the inverse of a specified bit in a general register or memory, and stores the result in the C flag. The bit number is specified by 3-bit immediate data.
Notes: * Size: Operand size B: Byte
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Section 2 CPU Instruction BXOR Size* B Function C ( of ) C XORs the C flag with a specified bit in a general register or memory, and stores the result in the C flag. BIXOR B C [~( of )] C XORs the C flag with the inverse of a specified bit in a general register or memory, and stores the result in the C flag. The bit number is specified by 3-bit immediate data. BLD BILD B B ( of ) C Copies a specified bit in a general register or memory to the C flag. ~ ( of ) C Copies the inverse of a specified bit in a general register or memory to the C flag. The bit number is specified by 3-bit immediate data. BST BIST B B C ( of ) Copies the C flag to a specified bit in a general register or memory. ~ C ( of ) Copies the inverse of the C flag to a specified bit in a general register or memory. The bit number is specified by 3-bit immediate data. Notes: * Size: Operand size B: Byte
Certain precautions are required in bit manipulation. See section 2.9.2, Notes on Bit Manipulation, for details.
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Section 2 CPU
BSET, BCLR, BNOT, BTST
15 8 7 0
op
15 8 7
IMM
rn
0
Operand: register direct (Rn) Bit No.: immediate (#xx:3) Operand: register direct (Rn) Bit No.: register direct (Rm)
0
op
15 8 7
rm
rn
op op
15 8 7
rn IMM
0 0
0 0
0 0
0 Operand: register indirect (@Rn) 0 Bit No.:
0
immediate (#xx:3)
op op
15 8 7
rn rm
0 0
0 0
0 0
0 Operand: register indirect (@Rn) 0 Bit No.:
0
register direct (Rm)
op op
15 8 7
abs IMM 0 0 0
Operand: absolute (@aa:8) 0 Bit No.:
0
immediate (#xx:3)
op op rm
abs 0 0 0
Operand: absolute (@aa:8) 0 Bit No.: register direct (Rm)
BAND, BOR, BXOR, BLD, BST
15 8 7 0
op
15 8 7
IMM
rn
0
Operand: register direct (Rn) Bit No.: immediate (#xx:3)
op op
15 8 7
rn IMM
0 0
0 0
0 0
0 Operand: register indirect (@Rn) 0 Bit No.:
0
immediate (#xx:3)
op op IMM
abs 0 0 0
Operand: absolute (@aa:8) 0 Bit No.: immediate (#xx:3)
Legend: op: Operation field rm, rn: Register field abs: Absolute address IMM: Immediate data
Figure 2.7 Bit Manipulation Instruction Codes
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Section 2 CPU
BIAND, BIOR, BIXOR, BILD, BIST
15 8 7 0
op
15 8 7
IMM
rn
0
Operand: register direct (Rn) Bit No.: immediate (#xx:3)
op op
15 8 7
rn IMM
0 0
0 0
0 0
0 Operand: register indirect (@Rn) 0 Bit No.:
0
immediate (#xx:3)
op op IMM
abs 0 0 0
Operand: absolute (@aa:8) 0 Bit No.: immediate (#xx:3)
Legend: op: Operation field rm, rn: Register field abs: Absolute address IMM: Immediate data
Figure 2.7 Bit Manipulation Instruction Codes (cont)
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Section 2 CPU
2.5.6
Branching Instructions
Table 2.9 describes the branching instructions. Figure 2.8 shows their object code formats. Table 2.9
Instruction Bcc
Branching Instructions
Size* Function Branches to the designated address if condition cc is true. The branching conditions are given below. Mnemonic BRA (BT) BRN (BF) BHI BLS BCC (BHS) BCS (BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE Description Always (true) Never (false) High Low or same Carry clear (high or same) Carry set (low) Not equal Equal Overflow clear Overflow set Plus Minus Greater or equal Less than Greater than Less or equal Condition Always Never CZ=0 CZ=1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV=0 NV=1 Z (N V) = 0 Z (N V) = 1
JMP BSR JSR RTS

Branches unconditionally to a specified address Branches to a subroutine at a specified address Branches to a subroutine at a specified address Returns from a subroutine
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Section 2 CPU
15 8 7 0
op
15
cc
8 7
disp
0
Bcc
op
15 8 7
rm
0
0
0
0
0
JMP (@Rm)
op abs
15 8 7 0
JMP (@aa:16)
op
15 8 7
abs
0
JMP (@@aa:8)
op
15 8 7
disp
0
BSR
op
15 8 7
rm
0
0
0
0
0
JSR (@Rm)
op abs
15 8 7 0
JSR (@aa:16)
op
15 8 7
abs
0
JSR (@@aa:8)
op Legend: op: Operation field cc: Condition field rm: Register field disp: Displacement abs: Absolute address
RTS
Figure 2.8 Branching Instruction Codes
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Section 2 CPU
2.5.7
System Control Instructions
Table 2.10 describes the system control instructions. Figure 2.9 shows their object code formats. Table 2.10 System Control Instructions
Instruction RTE SLEEP LDC Size* B Function Returns from an exception-handling routine Causes a transition from active mode to a power-down mode. See section 5, Power-Down Modes, for details. Rs CCR, #IMM CCR Moves immediate data or general register contents to the condition code register STC ANDC ORC XORC B B B B CCR Rd Copies the condition code register to a specified general register CCR #IMM CCR Logically ANDs the condition code register with immediate data CCR #IMM CCR Logically ORs the condition code register with immediate data CCR #IMM CCR Logically exclusive-ORs the condition code register with immediate data NOP PC + 2 PC Only increments the program counter Notes: * Size: Operand size B: Byte
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Section 2 CPU
15 8 7 0
op
15 8 7 0
RTE, SLEEP, NOP
op
15 8 7
rn
0
LDC, STC (Rn)
op
IMM
ANDC, ORC, XORC, LDC (#xx:8)
Legend: op: Operation field rn: Register field IMM: Immediate data
Figure 2.9 System Control Instruction Codes 2.5.8 Block Data Transfer Instruction
Table 2.11 describes the block data transfer instruction. Figure 2.10 shows its object code format. Table 2.11 Block Data Transfer Instruction
Instruction EEPMOV Size Function If R4L 0 then repeat @R5+ @R6+ R4L - 1 R4L until R4L = 0 else next; Block transfer instruction. Transfers the number of data bytes specified by R4L from locations starting at the address indicated by R5 to locations starting at the address indicated by R6. After the transfer, the next instruction is executed.
Certain precautions are required in using the EEPMOV instruction. See section 2.9.3, Notes on Use of the EEPMOV Instruction, for details.
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Section 2 CPU
15 8 7 0
op op Legend: op: Operation field
Figure 2.10 Block Data Transfer Instruction Code
2.6
Basic Operational Timing
CPU operation is synchronized by a system clock () or a subclock (SUB). For details on these clock signals see section 4, Clock Pulse Generators. The period from a rising edge of or SUB to the next rising edge is called one state. A bus cycle consists of two states or three states. The cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules. 2.6.1 Access to On-Chip Memory (RAM, ROM)
Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing access in byte or word size. Figure 2.11 shows the on-chip memory access cycle.
Bus cycle T1 state or SUB T2 state
Internal address bus
Address
Internal read signal Internal data bus (read access)
Read data
Internal write signal Internal data bus (write access)
Write data
Figure 2.11 On-Chip Memory Access Cycle
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Section 2 CPU
2.6.2
Access to On-Chip Peripheral Modules
On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits, so access is by byte size only. This means that for accessing word data, two instructions must be used. Two-State Access to On-Chip Peripheral Modules: Figure 2.12 shows the operation timing in the case of two-state access to an on-chip peripheral module.
Bus cycle T1 state or SUB T2 state
Internal address bus
Address
Internal read signal Internal data bus (read access)
Read data
Internal write signal Internal data bus (write access)
Write data
Figure 2.12 On-Chip Peripheral Module Access Cycle (2-State Access)
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Section 2 CPU
Three-State Access to On-Chip Peripheral Modules: Figure 2.13 shows the operation timing in the case of three-state access to an on-chip peripheral module.
Bus cycle T1 state or SUB T2 state T3 state
Internal address bus Internal read signal Internal data bus (read access) Internal write signal Internal data bus (write access)
Address
Read data
Write data
Figure 2.13 On-Chip Peripheral Module Access Cycle (3-State Access)
2.7
2.7.1
CPU States
Overview
There are four CPU states: the reset state, program execution state, program halt state, and exception-handling state. The program execution state includes active (high-speed or mediumspeed) mode and subactive mode. In the program halt state there are a sleep (high-speed or medium-speed) mode, standby mode, watch mode, and sub-sleep mode. These states are shown in figure 2.14. Figure 2.15 shows the state transitions.
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Section 2 CPU
CPU state
Reset state The CPU is initialized Program execution state
Active (high speed) mode The CPU executes successive program instructions at high speed, synchronized by the system clock Active (medium speed) mode The CPU executes successive program instructions at reduced speed, synchronized by the system clock Subactive mode The CPU executes successive program instructions at reduced speed, synchronized by the subclock
Low-power modes
Program halt state A state in which some or all of the chip functions are stopped to conserve power
Sleep (high-speed) mode Sleep (medium-speed) mode
Standby mode
Watch mode
Subsleep mode
Exceptionhandling state A transient state in which the CPU changes the processing flow due to a reset or an interrupt Note: See section 5, Power-Down Modes, for details on the modes and their transitions.
Figure 2.14 CPU Operation States
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Section 2 CPU
Reset cleared Reset state Reset occurs Exception-handling state
Reset occurs
Reset occurs
Interrupt source
Exception- Exceptionhandling handling request complete
Program halt state SLEEP instruction executed
Program execution state
Figure 2.15 State Transitions 2.7.2 Program Execution State
In the program execution state the CPU executes program instructions in sequence. There are three modes in this state, two active modes (high speed and medium speed) and one subactive mode. Operation is synchronized with the system clock in active mode (high speed and medium speed), and with the subclock in subactive mode. See section 5, Power-Down Modes for details on these modes. 2.7.3 Program Halt State
In the program halt state there are five modes: two sleep modes (high speed and medium speed), standby mode, watch mode, and subsleep mode. See section 5, Power-Down Modes for details on these modes. 2.7.4 Exception-Handling State
The exception-handling state is a transient state occurring when exception handling is started by a reset or interrupt and the CPU changes its normal processing flow. In exception handling caused by an interrupt, SP (R7) is referenced and the PC and CCR values are saved on the stack. For details on interrupt handling, see section 3.3, Interrupts.
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Section 2 CPU
2.8
Memory Map
Figure 2.16 shows a memory map of the H8/3644 Group.
H8/3640 Interrupt vectors 8 kbytes 12 kbytes 12 kbytes H8/3641 H8/3642 H8/3643 H8/3644
H'0000 H'002F H'0030 H'1FFF
H'2FFF 24 kbytes H'3FFF 32 kbytes
On-chip ROM H'5FFF
H'7FFF
Reserved
H'F770 H'F77F
Internal I/O registers (16 bytes) Reserved
H'FB80 H'FF7F H'FF80 H'FF7F H'FF80 H'FF9F H'FFA0 H'FFFF
On-chip RAM 512 bytes Reserved Internal I/O registers (128 bytes) 512 bytes 512 bytes 1 kbyte 1 kbyte
Figure 2.16 H8/3644 Group Memory Map
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Section 2 CPU
2.9
2.9.1
Application Notes
Notes on Data Access
1. Access to empty areas The address space of the H8/300L CPU includes empty areas in addition to the RAM, registers, and ROM areas available to the user. If these empty areas are mistakenly accessed by an application program, the following results will occur. Data transfer from CPU to empty area: The transferred data will be lost. This action may also cause the CPU to misoperate. Data transfer from empty area to CPU: Unpredictable data is transferred. 2. Access to internal I/O registers Internal data transfer to or from on-chip modules other than the ROM and RAM areas makes use of an 8-bit data width. If word access is attempted to these areas, the following results will occur. Word access from CPU to I/O register area: Upper byte: Will be written to I/O register. Lower byte: Transferred data will be lost. Word access from I/O register to CPU: Upper byte: Will be written to upper part of CPU register. Lower byte: Unpredictable data will be written to lower part of CPU register. Byte size instructions should therefore be used when transferring data to or from I/O registers other than the on-chip ROM and RAM areas. Figure 2.17 shows the data size and number of states in which on-chip peripheral modules can be accessed.
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Section 2 CPU
Access Word Byte States H'0000 H'002F H'0030 Interrupt vector area (48 bytes)
2 On-chip ROM
H'7FFF
Reserved
--
--
--
H'F770 Internal I/O registers (16 bytes) H'F77F Reserved H'FB80 On-chip RAM H'FF7F H'FF80 H'FF9F H'FFA0 Internal I/O registers (96 bytes) H'FFFF Notes: The H8/3644 is shown as an example. * Internal I/O registers in areas assigned to timer X (H'F770 to H'F77F), SCI3 (H'FFA8 to H'FFAD), and timer V (H'FFB8 to H'FFBD) are accessed in three states. x 2 or 3* Reserved -- -- -- 1,024 bytes 2 -- -- -- x 3*
Figure 2.17 Data Size and Number of States for Access to and from On-Chip Peripheral Modules
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Section 2 CPU
2.9.2
Notes on Bit Manipulation
The BSET, BCLR, BNOT, BST, and BIST instructions read one byte of data, modify the data, then write the data byte again. Special care is required when using these instructions in cases where two registers are assigned to the same address, in the case of registers that include writeonly bits, and when the instruction accesses an I/O port.
Order of Operation 1 2 3 Read Modify Write Operation Read byte data at the designated address Modify a designated bit in the read data Write the altered byte data to the designated address
Bit Manipulation in Two Registers Assigned to the Same Address Example 1: timer load register and timer counter Figure 2.18 shows an example in which two timer registers share the same address. When a bit manipulation instruction accesses the timer load register and timer counter of a reloadable timer, since these two registers share the same address, the following operations take place.
Order of Operation 1 2 3 Read Modify Write Operation Timer counter data is read (one byte) The CPU modifies (sets or resets) the bit designated in the instruction The altered byte data is written to the timer load register
The timer counter is counting, so the value read is not necessarily the same as the value in the timer load register. As a result, bits other than the intended bit in the timer load register may be modified to the timer counter value.
R Count clock Timer counter R: Read W: Write W Timer load register
Reload
Internal bus
Figure 2.18 Timer Configuration Example
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Section 2 CPU
Example 2: BSET instruction executed designating port 3 P37 and P36 are designated as input pins, with a low-level signal input at P37 and a high-level signal at P36. The remaining pins, P35 to P30, are output pins and output low-level signals. In this example, the BSET instruction is used to change pin P30 to high-level output. [A: Prior to executing BSET]
P37 Input/output Pin state PCR3 PDR3 Input Low level 0 1 P36 Input High level 0 0 P35 Output Low level 1 0 P34 Output Low level 1 0 P33 Output Low level 1 0 P32 Output Low level 1 0 P31 Output Low level 1 0 P30 Output Low level 1 0
[B: BSET instruction executed]
BSET #0 , @PDR3
The BSET instruction is executed designating port 3.
[C: After executing BSET]
P37 Input/output Pin state PCR3 PDR3 Input Low level 0 0 P36 Input High level 0 1 P35 Output Low level 1 0 P34 Output Low level 1 0 P33 Output Low level 1 0 P32 Output Low level 1 0 P31 Output Low level 1 0 P30 Output High level 1 1
[D: Explanation of how BSET operates] When the BSET instruction is executed, first the CPU reads port 3. Since P37 and P36 are input pins, the CPU reads the pin states (low-level and high-level input). P35 to P30 are output pins, so the CPU reads the value in PDR3. In this example PDR3 has a value of H'80, but the value read by the CPU is H'40. Next, the CPU sets bit 0 of the read data to 1, changing the PDR3 data to H'41. Finally, the CPU writes this value (H'41) to PDR3, completing execution of BSET.
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Section 2 CPU
As a result of this operation, bit 0 in PDR3 becomes 1, and P30 outputs a high-level signal. However, bits 7 and 6 of PDR3 end up with different values. To avoid this problem, store a copy of the PDR3 data in a work area in memory. Perform the bit manipulation on the data in the work area, then write this data to PDR3. [A: Prior to executing BSET]
MOV. B MOV. B MOV. B #80, R0L, R0L, P37 Input/output Pin state PCR3 PDR3 RAM0 Input Low level 0 1 1 R0L @RAM0 @PDR3 P36 Input High level 0 0 0
The PDR3 value (H'80) is written to a work area in memory (RAM0) as well as to PDR3.
P35 Output Low level 1 0 0 P34 Output Low level 1 0 0 P33 Output Low level 1 0 0 P32 Output Low level 1 0 0 P31 Output Low level 1 0 0 P30 Output Low level 1 0 0
[B: BSET instruction executed]
BSET #0 , @RAM0
The BSET instruction is executed designating the PDR3 work area (RAM0).
[C: After executing BSET]
MOV. B MOV. B @RAM0, R0L R0L, @PDR3 P37 Input/output Pin state PCR3 PDR3 RAM0 Input Low level 0 1 1 P36 Input High level 0 0 0
The work area (RAM0) value is written to PDR3.
P35 Output Low level 1 0 0
P34 Output Low level 1 0 0
P33 Output Low level 1 0 0
P32 Output Low level 1 0 0
P31 Output Low level 1 0 0
P30 Output High level 1 1 1
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Section 2 CPU
Bit Manipulation in a Register Containing a Write-Only Bit Example 3: BCLR instruction executed designating port 3 control register PCR3 As in the examples above, P37 and P36 are input pins, with a low-level signal input at P37 and a high-level signal at P36. The remaining pins, P35 to P30, are output pins that output low-level signals. In this example, the BCLR instruction is used to change pin P30 to an input port. It is assumed that a high-level signal will be input to this input pin. [A: Prior to executing BCLR]
P37 Input/output Pin state PCR3 PDR3 Input Low level 0 1 P36 Input High level 0 0 P35 Output Low level 1 0 P34 Output Low level 1 0 P33 Output Low level 1 0 P32 Output Low level 1 0 P31 Output Low level 1 0 P30 Output Low level 1 0
[B: BCLR instruction executed]
BCLR #0 , @PCR3
The BCLR instruction is executed designating PCR3.
[C: After executing BCLR]
P37 Input/output Pin state PCR3 PDR3 Output Low level 1 1 P36 Output High level 1 0 P35 Output Low level 1 0 P34 Output Low level 1 0 P33 Output Low level 1 0 P32 Output Low level 1 0 P31 Output Low level 1 0 P30 Input High level 0 0
[D: Explanation of how BCLR operates] When the BCLR instruction is executed, first the CPU reads PCR3. Since PCR3 is a write-only register, the CPU reads a value of H'FF, even though the PCR3 value is actually H'3F. Next, the CPU clears bit 0 in the read data to 0, changing the data to H'FE. Finally, this value (H'FE) is written to PCR3 and BCLR instruction execution ends.
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Section 2 CPU
As a result of this operation, bit 0 in PCR3 becomes 0, making P30 an input port. However, bits 7 and 6 in PCR3 change to 1, so that P37 and P36 change from input pins to output pins. To avoid this problem, store a copy of the PCR3 data in a work area in memory. Perform the bit manipulation on the data in the work area, then write this data to PCR3. [A: Prior to executing BCLR]
MOV. B MOV. B MOV. B #3F, R0L, R0L, P37 Input/output Pin state PCR3 PDR3 RAM0 Input Low level 0 1 0 R0L @RAM0 @PCR3 P36 Input High level 0 0 0
The PCR3 value (H'3F) is written to a work area in memory (RAM0) as well as to PCR3.
P35 Output Low level 1 0 1 P34 Output Low level 1 0 1 P33 Output Low level 1 0 1 P32 Output Low level 1 0 1 P31 Output Low level 1 0 1 P30 Output Low level 1 0 1
[B: BCLR instruction executed]
BCLR #0 , @RAM0
The BCLR instruction is executed designating the PCR3 work area (RAM0).
[C: After executing BCLR]
MOV. B MOV. B @RAM0, R0L R0L, @PCR3 P37 Input/output Pin state PCR3 PDR3 RAM0 Input Low level 0 1 0 P36 Input High level 0 0 0
The work area (RAM0) value is written to PCR3.
P35 Output Low level 1 0 1 P34 Output Low level 1 0 1 P33 Output Low level 1 0 1 P32 Output Low level 1 0 1 P31 Output Low level 1 0 1 P30 Output High level 0 0 0
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Section 2 CPU
Table 2.12 lists the pairs of registers that share identical addresses. Table 2.13 lists the registers that contain write-only bits. Table 2.12 Registers with Shared Addresses
Register Name Abbreviation Address
Output compare register AH and output compare register BH (timer X) OCRAH/OCRBH H'F774 Output compare register AL and output compare register BL (timer X) OCRAL/OCRBL H'F775 Timer counter B1 and timer load register B1 (timer B1) Port data register 1* Port data register 2* Port data register 3* Port data register 5* Port data register 6* Port data register 7* Port data register 8* Port data register 9* Note: * Port data registers have the same addresses as input pins. TCB1/TLB1 PDR1 PDR2 PDR3 PDR5 PDR6 PDR7 PDR8 PDR9 H'FFB3 H'FFD4 H'FFD5 H'FFD6 H'FFD8 H'FFD9 H'FFDA H'FFDB H'FFDC
Table 2.13 Registers with Write-Only Bits
Register Name Port control register 1 Port control register 2 Port control register 3 Port control register 5 Port control register 6 Port control register 7 Port control register 8 Port control register 9 PWM control register PWM data register U PWM data register L Abbreviation PCR1 PCR2 PCR3 PCR5 PCR6 PCR7 PCR8 PCR9 PWCR PWDRU PWDRL Address H'FFE4 H'FFE5 H'FFE6 H'FFE8 H'FFE9 H'FFEA H'FFEB H'FFEC H'FFD0 H'FFD1 H'FFD2
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Section 2 CPU
2.9.3
Notes on Use of the EEPMOV Instruction
* The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes specified by R4L from the address specified by R5 to the address specified by R6.
R5 R6
R5 + R4L
R6 + R4L
* When setting R4L and R6, make sure that the final destination address (R6 + R4L) does not exceed H'FFFF. The value in R6 must not change from H'FFFF to H'0000 during execution of the instruction.
R5 R6
R5 + R4L
H'FFFF Not allowed
R6 + R4L
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Section 3 Exception Handling
Section 3 Exception Handling
3.1 Overview
Exception handling is performed in the H8/3644 Group when a reset or interrupt occurs. Table 3.1 shows the priorities of these two types of exception handling. Table 3.1
Priority High
Exception Handling Types and Priorities
Exception Source Reset Interrupt Time of Start of Exception Handling Exception handling starts as soon as the reset state is cleared When an interrupt is requested, exception handling starts after execution of the present instruction or the exception handling in progress is completed
Low
3.2
3.2.1
Reset
Overview
A reset is the highest-priority exception. The internal state of the CPU and the registers of the onchip peripheral modules are initialized. 3.2.2 Reset Sequence
Reset by RES Pin: As soon as the RES pin goes low, all processing is stopped and the chip enters the reset state. To make sure the chip is reset properly, observe the following precautions. * At power on: Hold the RES pin low until the clock pulse generator output stabilizes. * Resetting during operation: Hold the RES pin low for at least 10 system clock cycles. Reset exception handling begins when the RES pin is held low for a given period, then returned to the high level.
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Section 3 Exception Handling
Reset exception handling takes place as follows. * The CPU internal state and the registers of on-chip peripheral modules are initialized, with the I bit of the condition code register (CCR) set to 1. * The PC is loaded from the reset exception handling vector address (H'0000 to H'0001), after which the program starts executing from the address indicated in PC. When system power is turned on or off, the RES pin should be held low. Figure 3.1 shows the reset sequence starting from RES input.
Reset cleared Program initial instruction prefetch Vector fetch Internal processing RES
Internal address bus Internal read signal Internal write signal Internal data bus (16-bit)
(1)
(2)
(2)
(3)
(1) Reset exception handling vector address (H'0000) (2) Program start address (3) First instruction of program
Figure 3.1 Reset Sequence
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Section 3 Exception Handling
Reset by Watchdog Timer: The watchdog timer counter (TCW) starts counting up when the WDON bit is set to 1 in the watchdog timer control/status register (TCSRW). If TCW overflows, the WRST bit is set to 1 in TCSRW and the chip enters the reset state. While the WRST bit is set to 1 in TCSRW, when TCW overflows the reset state is cleared and reset exception handling begins. The same reset exception handling is carried out as for input at the RES pin. For details on the watchdog timer, see section 9.6, Watchdog Timer. 3.2.3 Interrupt Immediately after Reset
After a reset, if an interrupt were to be accepted before the stack pointer (SP: R7) was initialized, PC and CCR would not be pushed onto the stack correctly, resulting in program runaway. To prevent this, immediately after reset exception handling all interrupts are masked. For this reason, the initial program instruction is always executed immediately after a reset. This instruction should initialize the stack pointer (e.g. MOV.W #xx: 16, SP).
3.3
3.3.1
Interrupts
Overview
The interrupt sources include 12 external interrupts (IRQ3 to IRQ0, INT7 to INT0) and 21 internal interrupts from on-chip peripheral modules. Table 3.2 shows the interrupt sources, their priorities, and their vector addresses. When more than one interrupt is requested, the interrupt with the highest priority is processed. The interrupts have the following features: * Internal and external interrupts can be masked by the I bit in CCR. When the I bit is set to 1, interrupt request flags can be set but the interrupts are not accepted. * IRQ3 to IRQ0 and INT7 to INT0 can be set independently to either rising edge sensing or falling edge sensing.
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Section 3 Exception Handling
Table 3.2
RES IRQ0 IRQ1 IRQ2 IRQ3 INT0 INT1 INT2 INT3 INT4 INT5 INT6 INT7 Timer A Timer B1 Timer X
Interrupt Sources and Their Priorities
Interrupt Reset IRQ0 IRQ1 IRQ2 IRQ3 INT0 INT1 INT2 INT3 INT4 INT5 INT6 INT7 Timer A overflow Timer B1 overflow Timer X input capture A Timer X input capture B Timer X input capture C Timer X input capture D Timer X compare match A Timer X compare match B Timer X overflow 10 11 16 H'0014 to H'0015 H'0016 to H'0017 H'0020 to H'0021 Vector Number 0 4 5 6 7 8 Vector Address H'0008 to H'0009 H'000A to H'000B H'000C to H'000D H'000E to H'000F H'0010 to H'0011 Priority H'0000 to H'0001 High
Interrupt Source
Timer V
Timer V compare match A Timer V compare match B Timer V overflow
17
H'0022 to H'0023
SCI1 SCI3
SCI1 transfer complete SCI3 transmit end SCI3 transmit data empty SCI3 receive data full SCI3 overrun error SCI3 framing error SCI3 parity error
19 21
H'0026 to H'0027 H'002A to H'002B
A/D (SLEEP instruction executed)
A/D conversion end Direct transfer
22 23
H'002C to H'002D H'002E to H'002F Low
Note: Vector addresses H'0002 to H'0007, H'0012 to H'0013, H'0018 to H'001F, H'0024 to H'0025, H'0028 to H'0029 are reserved and cannot be used. Rev. 6.00 Sep 12, 2006 page 62 of 526 REJ09B0326-0600
Section 3 Exception Handling
3.3.2
Interrupt Control Registers
Table 3.3 lists the registers that control interrupts. Table 3.3
Name Interrupt edge select register 1 Interrupt edge select register 2 Interrupt enable register 1 Interrupt enable register 2 Interrupt enable register 3 Interrupt request register 1 Interrupt request register 2 Interrupt request register 3 Note: *
Interrupt Control Registers
Abbreviation IEGR1 IEGR2 IENR1 IENR2 IENR3 IRR1 IRR2 IRR3 R/W R/W R/W R/W R/W R/W R/W * R/W * R/W * Initial Value H'70 H'00 H'10 H'00 H'00 H'10 H'00 H'00 Address H'FFF2 H'FFF3 H'FFF4 H'FFF5 H'FFF6 H'FFF7 H'FFF8 H'FFF9
Write is enabled only for writing of 0 to clear a flag.
Interrupt Edge Select Register 1 (IEGR1)
Bit Initial value Read/Write 7 0 6 1 5 1 4 1 3 IEG3 0 R/W 2 IEG2 0 R/W 1 IEG1 0 R/W 0 IEG0 0 R/W
IEGR1 is an 8-bit read/write register used to designate whether pins IRQ3 to IRQ0 are set to rising edge sensing or falling edge sensing. Upon reset, IEGR1 is initialized to H'70. Bit 7Reserved Bit: Bit 7 is reserved: it is always read as 0 and cannot be modified. Bits 6 to 4Reserved Bits: Bits 6 to 4 are reserved; they are always read as 1, and cannot be modified. Bit 3IRQ3 Edge Select (IEG3): Bit 3 selects the input sensing of pin IRQ3.
Bit 3: IEG3 0 1 Description Falling edge of IRQ3 pin input is detected Rising edge of IRQ3 pin input is detected (initial value)
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Section 3 Exception Handling
Bit 2IRQ2 Edge Select (IEG2): Bit 2 selects the input sensing of pin IRQ2.
Bit 2: IEG2 0 1 Description Falling edge of IRQ2 pin input is detected Rising edge of IRQ2 pin input is detected (initial value)
Bit 1IRQ1 Edge Select (IEG1): Bit 1 selects the input sensing of pin IRQ1.
Bit 1: IEG1 0 1 Description Falling edge of IRQ1 pin input is detected Rising edge of IRQ1 pin input is detected (initial value)
Bit 0IRQ0 Edge Select (IEG0): Bit 0 selects the input sensing of pin IRQ0.
Bit 0: IEG0 0 1 Description Falling edge of IRQ0 pin input is detected Rising edge of IRQ0 pin input is detected (initial value)
Interrupt Edge Select Register 2 (IEGR2)
Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
INTEG7 INTEG6 INTEG5 INTEG4 INTEG3 INTEG2 INTEG1 INTEG0
IEGR2 is an 8-bit read/write register, used to designate whether pins INT7 to INT0, and TMIB are set to rising edge sensing or falling edge sensing. Upon reset, IEGR2 is initialized to H'00. Bit 7INT7 Edge Select (INTEG7): Bit 7 selects the input sensing of the INT7 pin.
Bit 7: INTEG7 0 1 Description Falling edge of INT7 pin input is detected Rising edge of INT7 pin input is detected (initial value)
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Section 3 Exception Handling
Bit 6INT6 Edge Select (INTEG6): Bit 6 selects the input sensing of the INT6 pin and TMIB pin.
Bit 6: INTEG6 0 1 Description Falling edge of INT6 and TMIB pin input is detected Rising edge of INT6 and TMIB pin input is detected (initial value)
Bit 5INT5 Edge Select (INTEG5): Bit 5 selects the input sensing of the INT5 pin and ADTRG pin.
Bit 5: INTEG5 0 1 Description Falling edge of INT5 and ADTRG pin input is detected Rising edge of INT5 and ADTRG pin input is detected (initial value)
Bits 4 to 0INT4 to INT0 Edge Select (INTEG4 to INTEG0): Bits 4 to 0 select the input sensing of pins INT4 to INT0.
Bit n: INTEGn 0 1 Description Falling edge of INTn pin input is detected Rising edge of INTn pin input is detected (n = 4 to 0) (initial value)
Interrupt Enable Register 1 (IENR1)
Bit Initial value Read/Write 7 IENTB1 0 R/W 6 IENTA 0 R/W 5 0 4 1 3 IEN3 0 R/W 2 IEN2 0 R/W 1 IEN1 0 R/W 0 IEN0 0 R/W
IENR1 is an 8-bit read/write register that enables or disables interrupt requests. Upon reset, IENR1 is initialized to H'10. Bit 7Timer B1 Interrupt Enable (IENTB1): Bit 7 enables or disables timer B1 overflow interrupt requests.
Bit 7: IENTB1 0 1 Description Disables timer B1 interrupt requests Enables timer B1 interrupt requests Rev. 6.00 Sep 12, 2006 page 65 of 526 REJ09B0326-0600 (initial value)
Section 3 Exception Handling
Bit 6Timer A Interrupt Enable (IENTA): Bit 6 enables or disables timer A overflow interrupt requests.
Bit 6: IENTA 0 1 Description Disables timer A interrupt requests Enables timer A interrupt requests (initial value)
Bit 5Reserved Bit: Bit 5 is reserved: it is always read as 0 and cannot be modified. Bit 4Reserved Bit: Bit 4 is reserved; it is always read as 1, and cannot be modified. Bits 3 to 0IRQ3 to IRQ0 Interrupt Enable (IEN3 to IEN0): Bits 3 to 0 enable or disable IRQ3 to IRQ0 interrupt requests.
Bit n: IENn 0 1 Description Disables interrupt requests from pin IRQn Enables interrupt requests from pin IRQn (n = 3 to 0) (initial value)
Interrupt Enable Register 2 (IENR2)
Bit Initial value Read/Write 7 IENDT 0 R/W 6 IENAD 0 R/W 5 0 4 IENS1 0 R/W 3 0 2 0 1 0 0 0
IENR2 is an 8-bit read/write register that enables or disables interrupt requests. Upon reset, IENR2 is initialized to H'00. Bit 7Direct Transfer Interrupt Enable (IENDT): Bit 7 enables or disables direct transfer interrupt requests.
Bit 7: IENDT 0 1 Description Disables direct transfer interrupt requests Enables direct transfer interrupt requests (initial value)
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Section 3 Exception Handling
Bit 6A/D Converter Interrupt Enable (IENAD): Bit 6 enables or disables A/D converter interrupt requests.
Bit 6: IENAD 0 1 Description Disables A/D converter interrupt requests Enables A/D converter interrupt requests (initial value)
Bit 5Reserved Bit: Bit 5 is reserved: it is always read as 0 and cannot be modified. Bit 4SCI1 Interrupt Enable (IENS1): Bit 4 enables or disables SCI1 transfer complete interrupt requests.
Bit 4: IENS1 0 1 Description Disables SCI1 interrupt requests Enables SCI1 interrupt requests (initial value)
Bits 3 to 0Reserved Bits: Bits 3 to 0 are reserved: they are always read as 0 and cannot be modified. Interrupt Enable Register 3 (IENR3)
Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 INTEN5 0 R/W 4 INTEN4 0 R/W 3 INTEN3 0 R/W 2 INTEN2 0 R/W 1 0 R/W 0 0 R/W
INTEN7 INTEN6
INTEN1 INTEN0
IENR3 is an 8-bit read/write register that enables or disables INT7 to INT0 interrupt requests. Upon reset, IENR3 is initialized to H'00. Bits 7 to 0INT7 to INT0 Interrupt Enable (INTEN7 to INTEN0): Bits 7 to 0 enable or disable INT7 to INT0 interrupt requests.
Bit n: INTENn 0 1 Description Disables interrupt requests from pin INTn Enables interrupt requests from pin INTn (n = 7 to 0) (initial value)
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Section 3 Exception Handling
Interrupt Request Register 1 (IRR1)
Bit Initial value Read/Write Note: * 7 IRRTB1 0 R/W * 6 IRRTA 0 R/W * 5 0 4 1 3 IRRI3 0 R/W * 2 IRRI2 0 R/W * 1 IRRI1 0 R/W * 0 IRRI0 0 R/W *
Only a write of 0 for flag clearing is possible.
IRR1 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a timer B1, timer A, or IRQ3 to IRQ0 interrupt is requested. The flags are not cleared automatically when an interrupt is accepted. It is necessary to write 0 to clear each flag. Upon reset, IRR1 is initialized to H'10. Bit 7Timer B1 Interrupt Request Flag (IRRTB1)
Bit 7: IRRTB1 0 1 Description Clearing condition: When IRRTB1 = 1, it is cleared by writing 0 Setting condition: When the timer B1 counter value overflows from H'FF to H'00 (initial value)
Bit 6Timer A Interrupt Request Flag (IRRTA)
Bit 6: IRRTA 0 1 Description Clearing condition: When IRRTA = 1, it is cleared by writing 0 Setting condition: When the timer A counter value overflows from H'FF to H'00 (initial value)
Bit 5Reserved Bit: Bit 5 is reserved: it is always read as 0 and cannot be modified. Bit 4Reserved Bit: Bit 4 is reserved; it is always read as 1, and cannot be modified.
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Section 3 Exception Handling
Bits 3 to 0IRQ3 to IRQ0 Interrupt Request Flags (IRRI3 to IRRI0)
Bit n: IRRIn 0 1 Description Clearing condition: When IRRIn = 1, it is cleared by writing 0 (initial value)
Setting condition: When pin IRQn is designated for interrupt input and the designated signal edge is input (n = 3 to 0)
Interrupt Request Register 2 (IRR2)
Bit Initial value Read/Write Note: * 7 IRRDT 0 R/W * 6 IRRAD 0 R/W * 5 0 4 IRRS1 0 R/W * 3 0 2 0 1 0 0 0
Only a write of 0 for flag clearing is possible.
IRR2 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a direct transfer, A/D converter, or SCI1 interrupt is requested. The flags are not cleared automatically when an interrupt is accepted. It is necessary to write 0 to clear each flag. Upon reset, IRR2 is initialized to H'00. Bit 7Direct Transfer Interrupt Request Flag (IRRDT)
Bit 7: IRRDT 0 1 Description Clearing condition: When IRRDT = 1, it is cleared by writing 0 (initial value)
Setting condition: When a direct transfer is made by executing a SLEEP instruction while DTON = 1 in SYSCR2
Bit 6A/D Converter Interrupt Request Flag (IRRAD)
Bit 6: IRRAD 0 1 Description Clearing condition: When IRRAD = 1, it is cleared by writing 0 (initial value)
Setting condition: When A/D conversion is completed and ADSF is cleared to 0 in ADSR
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Section 3 Exception Handling
Bit 5Reserved bit: Bit 5 is reserved: it is always read as 0 and cannot be modified. Bit 4SCI1 Interrupt Request Flag (IRRS1)
Bit 4: IRRS1 0 1 Description Clearing condition: When IRRS1 = 1, it is cleared by writing 0 Setting condition: When an SCI1 transfer is completed (initial value)
Bits 3 to 0Reserved Bits: Bits 3 to 0 are reserved: they are always read as 0 and cannot be modified. Interrupt Request Register 3 (IRR3)
Bit Initial value Read/Write Note: * 7 INTF7 0 R/W * 6 INTF6 0 R/W * 5 INTF5 0 R/W * 4 INTF4 0 R/W * 3 INTF3 0 R/W * 2 INTF2 0 R/W * 1 INTF1 0 R/W * 0 INTF0 0 R/W *
Only a write of 0 for flag clearing is possible.
IRR3 is an 8-bit read/write register, in which a corresponding flag is set to 1 by a transition at pin INT7 to INT0. The flags are not cleared automatically when an interrupt is accepted. It is necessary to write 0 to clear each flag. Upon reset, IRR3 is initialized to H'00. Bits 7 to 0INT7 to INT0 Interrupt Request Flags (INTF7 to INTF0)
Bit n: INTFn 0 1 Description Clearing condition: When INTFn = 1, it is cleared by writing 0 Setting condition: When the designated signal edge is input at pin INTn (n = 7 to 0) (initial value)
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Section 3 Exception Handling
3.3.3
External Interrupts
There are 12 external interrupts: IRQ3 to IRQ0 and INT7 to INT0. Interrupts IRQ3 to IRQ0: Interrupts IRQ3 to IRQ0 are requested by input signals to pins IRQ3 to IRQ0. These interrupts are detected by either rising edge sensing or falling edge sensing, depending on the settings of bits IEG3 to IEG0 in IEGR1. When these pins are designated as pins IRQ3 to IRQ0 in port mode register 1 and the designated edge is input, the corresponding bit in IRR1 is set to 1, requesting an interrupt. Recognition of these interrupt requests can be disabled individually by clearing bits IEN3 to IEN0 to 0 in IENR1. These interrupts can all be masked by setting the I bit to 1 in CCR. When IRQ3 to IRQ0 interrupt exception handling is initiated, the I bit is set to 1 in CCR. Vector numbers 7 to 4 are assigned to interrupts IRQ3 to IRQ0. The order of priority is from IRQ0 (high) to IRQ3 (low). Table 3.2 gives details. INT Interrupts: INT interrupts are requested by input signals to pins INT7 to INT0. These interrupts are detected by either rising edge sensing or falling edge sensing, depending on the settings of bits INTEG7 to INTEG0 in IEGR2. When the designated edge is input at pins INT7 to INT0, the corresponding bit in IRR3 is set to 1, requesting an interrupt. Recognition of these interrupt requests can be disabled individually by clearing bits INTEN7 to INTEN0 to 0 in IENR3. These interrupts can all be masked by setting the I bit to 1 in CCR. When INT interrupt exception handling is initiated, the I bit is set to 1 in CCR. Vector number 8 is assigned to the INT interrupts. All eight interrupts have the same vector number, so the interrupthandling routine must discriminate the interrupt source. Note: Pins INT7 to INT0 are multiplexed with port 5. Even in port usage of these pins, whenever the designated edge is input or output, the corresponding bit INTFn is set to 1.
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Section 3 Exception Handling
3.3.4
Internal Interrupts
There are 21 internal interrupts that can be requested by the on-chip peripheral modules. When a peripheral module requests an interrupt, the corresponding bit in IRR1 or IRR2 is set to 1. Recognition of individual interrupt requests can be disabled by clearing the corresponding bit in IENR1 or IENR2 to 0. All these interrupts can be masked by setting the I bit to 1 in CCR. When internal interrupt handling is initiated, the I bit is set to 1 in CCR. Vector numbers from 23 to 9 are assigned to these interrupts. Table 3.2 shows the order of priority of interrupts from on-chip peripheral modules. 3.3.5 Interrupt Operations
Interrupts are controlled by an interrupt controller. Figure 3.2 shows a block diagram of the interrupt controller. Figure 3.3 shows the flow up to interrupt acceptance.
Interrupt controller
External or internal interrupts
Priority decision logic
Interrupt request
External interrupts or internal interrupt enable signals
I
CCR (CPU)
Figure 3.2 Block Diagram of Interrupt Controller
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Section 3 Exception Handling
Interrupt operation is described as follows. * If an interrupt occurs while the interrupt enable register bit is set to 1, an interrupt request signal is sent to the interrupt controller. * When the interrupt controller receives an interrupt request, it sets the interrupt request flag. * From among the interrupts with interrupt request flags set to 1, the interrupt controller selects the interrupt request with the highest priority and holds the others pending. (Refer to table 3.2 for a list of interrupt priorities.) * The interrupt controller checks the I bit of CCR. If the I bit is 0, the selected interrupt request is accepted; if the I bit is 1, the interrupt request is held pending. * If the interrupt is accepted, after processing of the current instruction is completed, both PC and CCR are pushed onto the stack. The state of the stack at this time is shown in figure 3.4. The PC value pushed onto the stack is the address of the first instruction to be executed upon return from interrupt handling. * The I bit of CCR is set to 1, masking further interrupts. * The vector address corresponding to the accepted interrupt is generated, and the interrupt handling routine located at the address indicated by the contents of the vector address is executed. Notes: 1. When disabling interrupts by clearing bits in an interrupt enable register, or when clearing bits in an interrupt request register, always do so while interrupts are masked (I = 1). 2. If the above clear operations are performed while I = 0, and as a result a conflict arises between the clear instruction and an interrupt request, exception processing for the interrupt will be executed after the clear instruction has been executed.
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Section 3 Exception Handling
Program execution state
IRRI0 = 1 Yes IEN0 = 1 Yes
No
No No
IRRI1 = 1 Yes IEN1 = 1 Yes
No No
IRRI2 = 1 Yes IEN2 = 1 Yes
No
IRRDT = 1 Yes IENDT = 1 Yes No
No
No
I=0 Yes PC contents saved CCR contents saved I1 Branch to interrupt handling routine
Legend: PC: Program counter CCR: Condition code register I bit of CCR I:
Figure 3.3 Flow up to Interrupt Acceptance
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Section 3 Exception Handling
SP - 4 SP - 3 SP - 2 SP - 1 SP (R7) Stack area
SP (R7) SP + 1 SP + 2 SP + 3 SP + 4
CCR CCR PCH PCL Even address
Prior to start of interrupt exception handling
PC and CCR saved to stack
After completion of interrupt exception handling
Legend: PCH: Upper 8 bits of program counter (PC) PCL: Lower 8 bits of program counter (PC) CCR: Condition code register SP: Stack pointer Notes: 1. PC shows the address of the first instruction to be executed upon return from the interrupt handling routine. 2. Register contents must always be saved and restored by word access, starting from an even-numbered address.
Figure 3.4 Stack State after Completion of Interrupt Exception Handling Figure 3.5 shows a typical interrupt sequence where the program area is in the on-chip ROM and the stack area is in the on-chip RAM.
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Interrupt is accepted
Interrupt level decision and wait for end of instruction Instruction prefetch Internal processing Stack access Vector fetch
Prefetch instruction of Internal interrupt-handling routine processing
Section 3 Exception Handling
Interrupt request signal
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(1) (3) (5) (6) (8) (9) (2) (4) (1) (7) (9) (10)
Internal address bus
Internal read signal
Internal write signal
Figure 3.5 Interrupt Sequence
Internal data bus (16 bits)
(1) Instruction prefetch address (Instruction is not executed. Address is saved as PC contents, becoming return address.) (2)(4) Instruction code (not executed) (3) Instruction prefetch address (Instruction is not executed.) (5) SP - 2 (6) SP - 4 (7) CCR (8) Vector address (9) Starting address of interrupt-handling routine (contents of vector) (10) First instruction of interrupt-handling routine
Section 3 Exception Handling
3.3.6
Interrupt Response Time
Table 3.4 shows the number of wait states after an interrupt request flag is set until the first instruction of the interrupt handler is executed. Table 3.4
Item Waiting time for completion of executing instruction* Saving of PC and CCR to stack Vector fetch Instruction fetch Internal processing Total Note: * Not including EEPMOV instruction.
Interrupt Wait States
States 1 to 13 4 2 4 4 15 to 27
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Section 3 Exception Handling
3.4
3.4.1
Application Notes
Notes on Stack Area Use
When word data is accessed in the H8/3644 Group, the least significant bit of the address is regarded as 0. Access to the stack always takes place in word size, so the stack pointer (SP: R7) should never indicate an odd address. Use PUSH Rn (MOV.W Rn, @-SP) or POP Rn (MOV.W @SP+, Rn) to save or restore register values. Setting an odd address in SP may cause a program to crash. An example is shown in figure 3.6.
SP SP
PCH PC L
SP
R1L PC L
H'FEFC H'FEFD H'FEFF
BSR instruction SP set to H'FEFF
MOV. B R1L, @-R7 Contents of PCH are lost
Stack accessed beyond SP
Legend: PCH: Upper byte of program counter PCL: Lower byte of program counter R1L: General register R1L SP: Stack pointer
Figure 3.6 Operation when Odd Address Is Set in SP When CCR contents are saved to the stack during interrupt exception handling or restored when RTE is executed, this also takes place in word size. Both the upper and lower bytes of word data are saved to the stack; on return, the even address contents are restored to CCR while the odd address contents are ignored.
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Section 3 Exception Handling
3.4.2
Notes on Rewriting Port Mode Registers
When a port mode register is rewritten to switch the functions of external interrupt pins, the following points should be observed. When an external interrupt pin function is switched by rewriting the port mode register that controls pins IRQ3 to IRQ1, the interrupt request flag may be set to 1 at the time the pin function is switched, even if no valid interrupt is input at the pin. Table 3.5 shows the conditions under which interrupt request flags are set to 1 in this way. Table 3.5 Conditions under which Interrupt Request Flag Is Set to 1
Conditions When PMR1 bit IRQ3 is changed from 0 to 1 while pin IRQ3 is low and IEGR bit IEG3 = 0. When PMR1 bit IRQ3 is changed from 1 to 0 while pin IRQ3 is low and IEGR bit IEG3 = 1. IRRI2 When PMR1 bit IRQ2 is changed from 0 to 1 while pin IRQ2 is low and IEGR bit IEG2 = 0. When PMR1 bit IRQ2 is changed from 1 to 0 while pin IRQ2 is low and IEGR bit IEG2 = 1. IRRI1 When PMR1 bit IRQ1 is changed from 0 to 1 while pin IRQ1 is low and IEGR bit IEG1 = 0. When PMR1 bit IRQ1 is changed from 1 to 0 while pin IRQ1 is low and IEGR bit IEG1 = 1.
Interrupt Request Flags Set to 1 IRR1 IRRI3
Figure 3.7 shows the procedure for setting a bit in a port mode register and clearing the interrupt request flag. When switching a pin function, mask the interrupt before setting the bit in the port mode register. After accessing the port mode register, execute at least one instruction (e.g., NOP), then clear the interrupt request flag from 1 to 0. If the instruction to clear the flag is executed immediately after the port mode register access without executing an intervening instruction, the flag will not be cleared. An alternative method is to avoid the setting of interrupt request flags when pin functions are switched by keeping the pins at the high level so that the conditions in table 3.5 do not occur.
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Section 3 Exception Handling
Interrupts masked. (Another possibility is to disable the relevant interrupt in interrupt enable register 1.)
CCR I bit 1
Set port mode register bit Execute NOP instruction Clear interrupt request flag to 0 After setting the port mode register bit, first execute at least one instruction (e.g., NOP), then clear the interrupt request flag to 0
CCR I bit 0
Interrupt mask cleared
Figure 3.7 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure
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Section 4 Clock Pulse Generators
Section 4 Clock Pulse Generators
4.1 Overview
Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a system clock pulse generator and a subclock pulse generator. The system clock pulse generator consists of a system clock oscillator and system clock dividers. The subclock pulse generator consists of a subclock oscillator circuit and a subclock divider. 4.1.1 Block Diagram
Figure 4.1 shows a block diagram of the clock pulse generators.
OSC 1 OSC 2
System clock oscillator
OSC (f OSC)
OSC/2
System clock divider (1/2)
OSC/128 System clock OSC/64 divider (1/64, 1/32, OSC/32 1/16, 1/8) OSC/16 W/2 W/4 W/8
Prescaler S (13 bits) /2 to /8192
System clock pulse generator X1 X2 Subclock oscillator
W (f W )
Subclock divider (1/2, 1/4, 1/8)
SUB W /2 W /4 W /8 to W /128
Subclock pulse generator
Prescaler W (5 bits)
Figure 4.1 Block Diagram of Clock Pulse Generators 4.1.2 System Clock and Subclock
The basic clock signals that drive the CPU and on-chip peripheral modules are and SUB. Four of the clock signals have names: is the system clock, SUB is the subclock, OSC is the oscillator clock, and W is the watch clock. The clock signals available for use by peripheral modules are /2, /4, /8, /16, /32, /64, /128, /256, /512, /1024, /2048, /4096, /8192, W/2, W/4, W/8, W/16, W/32, W/64, and W/128. The clock requirements differ from one module to another.
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Section 4 Clock Pulse Generators
4.2
System Clock Generator
Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic resonator, or by providing external clock input. Connecting a Crystal Resonator: Figure 4.2 shows a typical method of connecting a crystal resonator.
C1 OSC 1 Rf OSC 2 C2 R f = 1 M 20% C1 = C 2 = 12 pF 20%
Figure 4.2 Typical Connection to Crystal Resonator Figure 4.3 shows the equivalent circuit of a crystal resonator. An oscillator having the characteristics given in table 4.1 should be used.
CS LS OSC 1 RS OSC 2
C0
Figure 4.3 Equivalent Circuit of Crystal Resonator Table 4.1
Frequency RS (max) C0 (max)
Crystal Resonator Parameters
2 MHz 500 7 pF 4 MHz 100 7 pF 8 MHz 50 7 pF 10 MHz 30 7 pF
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Section 4 Clock Pulse Generators
Connecting a Ceramic Resonator: Figure 4.4 shows a typical method of connecting a ceramic resonator.
C1 OSC 1 Rf OSC 2 C2 R f = 1 M 20% C1 = 30 pF 10% C2 = 30 pF 10% Ceramic resonator: Murata
Figure 4.4 Typical Connection to Ceramic Resonator Notes on Board Design: When generating clock pulses by connecting a crystal or ceramic resonator, pay careful attention to the following points. Avoid running signal lines close to the oscillator circuit, since the oscillator may be adversely affected by induction currents. (See figure 4.5.) The board should be designed so that the oscillator and load capacitors are located as close as possible to pins OSC1 and OSC2.
To be avoided
Signal A Signal B
C2 OSC 1
OSC 2 C1
Figure 4.5 Board Design of Oscillator Circuit
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Section 4 Clock Pulse Generators
External Clock Input Method: Connect an external clock signal to pin OSC1, and leave pin OSC2 open. Figure 4.6 shows a typical connection.
OSC 1 OSC 2
External clock input
Open
Figure 4.6 External Clock Input (Example)
Frequency Duty cycle Oscillator Clock (OSC) 45% to 55%
4.3
Subclock Generator
Connecting a 32.768-kHz Crystal Resonator: Clock pulses can be supplied to the subclock divider by connecting a 32.768-kHz crystal resonator, as shown in figure 4.7. Follow the same precautions as noted under section 4.2, Notes on Board Design.
C1 X1 X2 C2
C1 = C 2 = 15 pF (typ.)
Figure 4.7 Typical Connection to 32.768-kHz Crystal Resonator
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Section 4 Clock Pulse Generators
Figure 4.8 shows the equivalent circuit of the 32.768-kHz crystal resonator.
CS LS X1 RS X2
C0
C0 = 1.5 pF (typ.) RS = 14 k (typ.) f W = 32.768 kHz Crystal resonator:MX38T (Nihon Denpa Kogyo)
Figure 4.8 Equivalent Circuit of 32.768-kHz Crystal Resonator Pin Connection when Not Using Subclock: When the subclock is not used, connect pin X1 to VCC and leave pin X2 open, as shown in figure 4.9.
VCC X1 X2 Open
Figure 4.9 Pin Connection when not Using Subclock
4.4
Prescalers
The H8/3644 Group is equipped with two on-chip prescalers having different input clocks (prescaler S and prescaler W). Prescaler S is a 13-bit counter using the system clock () as its input clock. Its prescaled outputs provide internal clock signals for on-chip peripheral modules. Prescaler W is a 5-bit counter using a 32.768-kHz signal divided by 4 (W/4) as its input clock. Its prescaled outputs are used by timer A as a time base for timekeeping. Prescaler S (PSS): Prescaler S is a 13-bit counter using the system clock () as its input clock. It is incremented once per clock period. Prescaler S is initialized to H'0000 by a reset, and starts counting on exit from the reset state.
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Section 4 Clock Pulse Generators
In standby mode, watch mode, subactive mode, and subsleep mode, the system clock pulse generator stops. Prescaler S also stops and is initialized to H'0000. The CPU cannot read or write prescaler S. The output from prescaler S is shared by the on-chip peripheral modules. The divider ratio can be set separately for each on-chip peripheral function. In active (medium-speed) mode the clock input to prescaler S is determined by the division factor designated by MA1 and MA0 in SYSCR1. Prescaler W (PSW): Prescaler W is a 5-bit counter using a 32.768 kHz signal divided by 4 (W/4) as its input clock. Prescaler W is initialized to H'00 by a reset, and starts counting on exit from the reset state. Even in standby mode, watch mode, subactive mode, or subsleep mode, prescaler W continues functioning so long as clock signals are supplied to pins X1 and X2. Prescaler W can be reset by setting 1s in bits TMA3 and TMA2 of timer mode register A (TMA). Output from prescaler W can be used to drive timer A, in which case timer A functions as a time base for timekeeping.
4.5
Note on Oscillators
Oscillator characteristics are closely related to board design and should be carefully evaluated by the user, referring to the examples shown in this section. Oscillator circuit constants will differ depending on the oscillator element, stray capacitance in its interconnecting circuit, and other factors. Suitable constants should be determined in consultation with the oscillator element manufacturer. Design the circuit so that the oscillator element never receives voltages exceeding its maximum rating.
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Section 5 Power-Down Modes
Section 5 Power-Down Modes
5.1 Overview
The H8/3644 Group has eight modes of operation after a reset. These include seven power-down modes, in which power dissipation is significantly reduced. Table 5.1 gives a summary of the eight operating modes. Table 5.1 Operating Modes
Description The CPU and all on-chip peripheral functions are operable on the system clock The CPU and all on-chip peripheral functions are operable on the system clock, but at 1/64, 1/32, 1/6, or 1/8* the speed in active (high-speed) mode The CPU, and the time-base function of timer A are operable on the subclock The CPU halts. On-chip peripheral functions except PWM are operable on the system clock The CPU halts. On-chip peripheral functions except PWM are operable on the system clock, but at 1/64, 1/32, 1/6, or 1/8* the speed in active (high-speed) mode The CPU halts. The time-base function of timer A are operable on the subclock The CPU halts. The time-base function of timer A is operable on the subclock The CPU and all on-chip peripheral functions halt
Operating Mode Active (high-speed) mode Active (medium-speed) mode
Subactive mode Sleep (high-speed) mode Sleep (medium-speed) mode
Subsleep mode Watch mode Standby mode Note: *
Determined by the value set in bits MA1 and MA0 of system control register 1 (SYSCR1).
Of these eight operating modes, all but the active (high-speed) mode are power-down modes. In this section the two active modes (high-speed and medium speed) will be referred to collectively as active mode, and the two sleep modes (high-speed and medium speed) will be referred to collectively as sleep mode. Figure 5.1 shows the transitions among these operation modes. Table 5.2 indicates the internal states in each mode.
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Section 5 Power-Down Modes
Program execution state Active (high-speed) mode
SLEEP instruction*g SLEEP instruction*f
Reset state
Program halt state SLEEP instruction*a
*3
* EP n LE ctio S ru st inin SL st E ru EP ct io n *b SLEEP instruction*b a
Program halt state
P EE n SL uctio tr ins
*4
*d
Sleep (high-speed) mode
Standby mode
SL instr EEP uctio *d n
*4
ins SLEE tru ctio P n *e
Active (medium-speed) mode
SLEEP instruction*h SLEEP instruction*i
*e EP n LE ctio S ru st in
*3
Sleep (medium-speed) mode
*1
*1
Watch mode
SLEEP instruction*e
*1
Subactive mode
ins SLEE t ru P ct i on *j SL ins E tru EP ctio n *i
SLEEP instruction*c
*2
Subsleep mode
Power-down modes Mode Transition Conditions (1) LSON MSON SSBY TMA3 DTON a b c d e f g h i J 0 0 1 0 0 1 0 0 0 1 1 0 0 1 1 1 Mode Transition Conditions (2) Interrupt Sources 1 2 3 4 Timer A interrupt, IRQ0 interrupt Timer a interrupt, IRQ3 to IRQ0 interrupts, INT interrupt All interrupts IRQ1 or IRQ0 interrupt
* *
1 0 1
*
0 0 0 1 0
* * *
0 1 1
0 0 0 0 0 1 1 1 1 1
* *
1 1 1
*
0
* Don't care
Notes: 1. A transition between different modes cannot be made to occur simply because an interrupt request is generated. Make sure that interrupt handling is performed after the interrupt is accepted. 2. Details on the mode transition conditions are given in the explanations of each mode, in sections 5.2 through 5.8.
Figure 5.1 Mode Transition Diagram
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Section 5 Power-Down Modes
Table 5.2
Internal State in Each Operating Mode
Active Mode Sleep Mode HighSpeed Functions Functions Halted Retained MediumSpeed Functions Functions Halted Retained Watch Mode Halted Functions Halted Retained Subactive Subsleep Mode Mode Halted Functions Functions Halted Functions Halted Retained Standby Mode Halted Functions Halted Retained
1 Retained*
Function System clock oscillator Subclock oscillator CPU operations Instructions Registers RAM I/O ports External interrupts IRQ0 IRQ1 IRQ2 IRQ3 INT0 INT1 INT2 INT3 INT4 INT5 INT6 INT7 Peripheral functions Timer A Timer B1 Timer V Timer X Watchdog timer SCI1 SCI3 PWM A/D converter
HighSpeed Functions Functions Functions
MediumSpeed Functions Functions Functions
Functions
Functions
Functions
Functions
Functions
2 Retained*
Functions
Functions
Functions Retained*2
Functions
Functions
Functions
Functions
2 Retained* Functions
Functions
2 Retained*
Functions
Functions
Functions
Functions
Functions*3 Functions*3 Functions*3 Retained Retained Reset Retained Reset Retained Reset Reset
Retained
Retained
Retained
Retained
Reset Retained Functions Retained Functions Retained
Reset Retained
Reset Retained
Reset Retained
Notes: 1. Register contents are retained, but output is high-impedance state. 2. External interrupt requests are ignored. Interrupt request register contents are not altered. 3. Functions if timekeeping time-base function is selected.
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Section 5 Power-Down Modes
5.1.1
System Control Registers
The operation mode is selected using the system control registers described in table 5.3. Table 5.3
Name System control register 1 System control register 2
System Control Registers
Abbreviation SYSCR1 SYSCR2 R/W R/W R/W Initial Value H'07 H'E0 Address H'FFF0 H'FFF1
System Control Register 1 (SYSCR1)
Bit Initial value Read/Write 7 SSBY 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 LSON 0 R/W 2 1 1 MA1 1 R/W 0 MA0 1 R/W
SYSCR1 is an 8-bit read/write register for control of the power-down modes. Upon reset, SYSCR1 is initialized to H'07. Bit 7Software Standby (SSBY): This bit designates transition to standby mode or watch mode.
Bit 7: SSBY 0 Description * * 1 * * When a SLEEP instruction is executed in active mode, a transition is made to sleep mode When a SLEEP instruction is executed in subactive mode, a transition is made to subsleep mode (initial value) When a SLEEP instruction is executed in active mode, a transition is made to standby mode or watch mode When a SLEEP instruction is executed in subactive mode, a transition is made to watch mode
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Section 5 Power-Down Modes
Bits 6 to 4Standby Timer Select 2 to 0 (STS2 to STS0): These bits designate the time the CPU and peripheral modules wait for stable clock operation after exiting from standby mode or watch mode to active mode due to an interrupt. The designation should be made according to the clock frequency so that the waiting time is at least 10 ms.
Bit 6: STS2 0 Bit 5: STS1 0 1 1 * Bit 4: STS0 0 1 0 1 * Legend: * Don't care Description Wait time = 8,192 states Wait time = 16,384 states Wait time = 32,768 states Wait time = 65,536 states Wait time = 131,072 states (initial value)
Bit 3Low Speed on Flag (LSON): This bit chooses the system clock () or subclock (SUB) as the CPU operating clock when watch mode is cleared. The resulting operation mode depends on the combination of other control bits and interrupt input.
Bit 3: LSON 0 1 Description The CPU operates on the system clock () The CPU operates on the subclock (SUB) (initial value)
Bits 2Reserved Bits: Bit 2 is reserved: it is always read as 1 and cannot be modified. Bits 1 and 0Active (Medium-Speed) Mode Clock Select (MA1, MA0): Bits 1 and 0 choose osc/128, osc/64, osc/32, or osc/16 as the operating clock in active (medium-speed) mode and sleep (medium-speed) mode. MA1 and MA0 should be written in active (high-speed) mode or subactive mode.
Bit 1: MA1 0 1 Bit 0: MA0 0 1 0 1 Description osc/16 osc/32 osc/64 osc/128 (initial value)
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Section 5 Power-Down Modes
System Control Register 2 (SYSCR2)
Bit Initial value Read/Write 7 1 6 1 5 1 4 NESEL 0 R/W 3 DTON 0 R/W 2 MSON 0 R/W 1 SA1 0 R/W 0 SA0 0 R/W
SYSCR2 is an 8-bit read/write register for power-down mode control. Upon reset, SYSCR2 is initialized to H'E0. Bits 7 to 5Reserved Bits: These bits are reserved; they are always read as 1, and cannot be modified. Bit 4Noise Elimination Sampling Frequency Select (NESEL): This bit selects the frequency at which the watch clock signal (W) generated by the subclock pulse generator is sampled, in relation to the oscillator clock (OSC) generated by the system clock pulse generator. When OSC = 2 to 10 MHz, clear NESEL to 0.
Bit 4: NESEL 0 1 Description Sampling rate is OSC/16 Sampling rate is OSC/4 (initial value)
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Section 5 Power-Down Modes
Bit 3Direct Transfer on Flag (DTON): This bit designates whether or not to make direct transitions among active (high-speed), active (medium-speed) and subactive mode when a SLEEP instruction is executed. The mode to which the transition is made after the SLEEP instruction is executed depends on a combination of this and other control bits.
Bit 3: DTON 0 Description * * 1 * When a SLEEP instruction is executed in active mode, a transition is made to standby mode, watch mode, or sleep mode When a SLEEP instruction is executed in subactive mode, a transition is made to watch mode or subsleep mode (initial value) When a SLEEP instruction is executed in active (high-speed) mode, a direct transition is made to active (medium-speed) mode if SSBY = 0, MSON = 1, and LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1 When a SLEEP instruction is executed in active (medium-speed) mode, a direct transition is made to active (high-speed) mode if SSBY = 0, MSON = 0, and LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON =1 When a SLEEP instruction is executed in subactive mode, a direct transition is made to active (high-speed) mode if SSBY = 1, TMA3 = 1, LSON = 0, and MSON = 0, or to active (medium-speed) mode if SSBY = 1, TMA3 = 1, LSON = 0, and MSON = 1
*
*
Bit 2Medium Speed on Flag (MSON): After standby, watch, or sleep mode is cleared, this bit selects active (high-speed), active (medium-speed), or sleep (medium-speed) mode.
Bit 2: MSON 0 Description * * 1 * * After standby, watch, or sleep mode is cleared, operation is in active (highspeed) mode When a SLEEP instruction is executed in active mode, a transition is made to sleep (high-speed) mode (initial value) After standby, watch, or sleep mode is cleared, operation is in active (medium-speed) mode When a SLEEP instruction is executed in active mode, a transition is made to sleep (medium-speed) mode
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Section 5 Power-Down Modes
Bits 1 and 0 Subactive Mode Clock Select (SA1 and SA0): These bits select the CPU clock rate (W/2, W/4, or W/8) in subactive mode. SA1 and SA0 cannot be modified in subactive mode.
Bit 1: SA1 0 1 Bit 0: SA0 0 1 * Legend: * Don't care Description W /8 W /4 W /2 (initial value)
5.2
5.2.1
Sleep Mode
Transition to Sleep Mode
Transition to Sleep (High-Speed) Mode: The system goes from active mode to sleep (highspeed) mode when a SLEEP instruction is executed while the SSBY and LSON bits in SYSCR1 and the MSON and DTON bits in SYSCR2 are all cleared to 0. In sleep (high-speed) mode CPU operation is halted but the on-chip peripheral functions other than PWM are operational. CPU register contents are retained. Transition to Sleep (Medium-Speed) Mode: The system goes from active mode to sleep (medium-speed) mode when a SLEEP instruction is executed while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is set to 1, and the DTON bit in SYSCR2 is cleared to 0. In sleep (medium-speed) mode, as in sleep (high-speed) mode, CPU operation is halted but the on-chip peripheral functions other than PWM are operational. The clock frequency in sleep (medium-speed) mode is determined by the MA1 and MA0 bits in SYSCR1. CPU register contents are retained. 5.2.2 Clearing Sleep Mode
Sleep mode is cleared by any interrupt (timer A, timer B1, timer X, timer V, IRQ3 to IRQ0, INT7 to INT0, SCI3, SCI1, or A/D converter), or by input at the RES pin. * Clearing by interrupt When an interrupt is requested, sleep mode is cleared and interrupt exception handling starts. A transition is made from sleep (high-speed) mode to active (high-speed) mode, or from sleep (medium-speed) mode to active (medium-speed) mode. Sleep mode is not cleared if the I bit of the condition code register (CCR) is set to 1 or the particular interrupt is disabled in the interrupt enable register.
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Section 5 Power-Down Modes
* Clearing by RES input When the RES pin goes low, the CPU goes into the reset state and sleep mode is cleared. 5.2.3 Clock Frequency in Sleep (Medium-Speed) Mode
Operation in sleep (medium-speed) mode is clocked at the frequency designated by the MA1 and MA0 bits in SYSCR1.
5.3
5.3.1
Standby Mode
Transition to Standby Mode
The system goes from active mode to standby mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, and bit TMA3 in TMA is cleared to 0. In standby mode the clock pulse generator stops, so the CPU and on-chip peripheral modules stop functioning, but as long as the rated voltage is supplied, the contents of CPU registers, on-chip RAM, and some on-chip peripheral module registers are retained. On-chip RAM contents will be further retained down to a minimum RAM data retention voltage. The I/O ports go to the high-impedance state. 5.3.2 Clearing Standby Mode
Standby mode is cleared by an interrupt (IRQ1 or IRQ0) or by input at the RES pin. * Clearing by interrupt When an interrupt is requested, the system clock pulse generator starts. After the time set in bits STS2-STS0 in SYSCR1 has elapsed, a stable system clock signal is supplied to the entire chip, standby mode is cleared, and interrupt exception handling starts. Operation resumes in active (high-speed) mode if MSON = 0 in SYSCR2, or active (medium-speed) mode if MSON = 1. Standby mode is not cleared if the I bit of CCR is set to 1 or the particular interrupt is disabled in the interrupt enable register. * Clearing by RES input When the RES pin goes low, the system clock pulse generator starts. After the pulse generator output has stabilized, if the RES pin is driven high, the CPU starts reset exception handling. Since system clock signals are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the RES pin should be kept at the low level until the pulse generator output stabilizes.
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Section 5 Power-Down Modes
5.3.3
Oscillator Settling Time after Standby Mode Is Cleared
Bits STS2 to STS0 in SYSCR1 should be set as follows. * When a crystal oscillator is used The table 5.4 gives settings for various operating frequencies. Set bits STS2 to STS0 for a waiting time of at least 10 ms. Table 5.4
STS2 0 0 0 0 1
Clock Frequency and Settling Time (times are in ms)
STS1 0 0 1 1 * STS0 0 1 0 1 * Waiting Time 8,192 states 16,384 states 32,768 states 65,536 states 131,072 states 5 MHz 1.6 3.2 6.6 13.1 26.2 4 MHz 2.0 4.1 8.2 16.4 32.8 2 MHz 4.1 8.2 16.4 32.8 65.5 1 MHz 8.2 16.4 32.8 65.5 131.1 0.5 MHz 16.4 32.8 65.5 131.1 262.1
Legend: * Don't care
* When an external clock is used Any values may be set. Normally the minimum time (STS2 = STS1 = STS0 = 0) should be set.
5.4
5.4.1
Watch Mode
Transition to Watch Mode
The system goes from active or subactive mode to watch mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1 and bit TMA3 in TMA is set to 1. In watch mode, operation of on-chip peripheral modules other than timer A is halted. As long as a minimum required voltage is applied, the contents of CPU registers, the on-chip RAM and some registers of the on-chip peripheral modules, are retained. I/O ports keep the same states as before the transition.
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Section 5 Power-Down Modes
5.4.2
Clearing Watch Mode
Watch mode is cleared by an interrupt (timer A or IRQ0) or by input at the RES pin. * Clearing by interrupt When watch mode is cleared by a timer A interrupt or IRQ0 interrupt, the mode to which a transition is made depends on the settings of LSON in SYSCR1 and MSON in SYSCR2. If both LSON and MSON are cleared to 0, transition is to active (high-speed) mode; if LSON = 0 and MSON = 1, transition is to active (medium-speed) mode; if LSON = 1, transition is to subactive mode. When the transition is to active mode, after the time set in SYSCR1 bits STS2 to STS0 has elapsed, a stable clock signal is supplied to the entire chip, watch mode is cleared, and interrupt exception handling starts. Watch mode is not cleared if the I bit of CCR is set to 1 or the particular interrupt is disabled in the interrupt enable register. * Clearing by RES input Clearing by RES pin is the same as for standby mode; see section 5.3.2, Clearing Standby Mode. 5.4.3 Oscillator Settling Time after Watch Mode Is Cleared
The waiting time is the same as for standby mode; see section 5.3.3, Oscillator Settling Time after Standby Mode Is Cleared.
5.5
5.5.1
Subsleep Mode
Transition to Subsleep Mode
The system goes from subactive mode to subsleep mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is cleared to 0, LSON bit in SYSCR1 is set to 1, and TMA3 bit in TMA is set to 1. In subsleep mode, operation of on-chip peripheral modules other than timer A is halted. As long as a minimum required voltage is applied, the contents of CPU registers, the onchip RAM and some registers of the on-chip peripheral modules are retained. I/O ports keep the same states as before the transition.
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Section 5 Power-Down Modes
5.5.2
Clearing Subsleep Mode
Subsleep mode is cleared by an interrupt (timer A, IRQ3 to IRQ0, INT7 to INT0) or by input at the RES pin. * Clearing by interrupt When an interrupt is requested, subsleep mode is cleared and interrupt exception handling starts. Subsleep mode is not cleared if the I bit of CCR is set to 1 or the particular interrupt is disabled in the interrupt enable register. * Clearing by RES input Clearing by RES pin is the same as for standby mode; see section 5.3.2, Clearing Standby Mode.
5.6
5.6.1
Subactive Mode
Transition to Subactive Mode
Subactive mode is entered from watch mode if a timer A or IRQ0 interrupt is requested while the LSON bit in SYSCR1 is set to 1. From subsleep mode, subactive mode is entered if a timer A, IRQ3 to IRQ0, or INT7 to INT0 interrupt is requested. A transition to subactive mode does not take place if the I bit of CCR is set to 1 or the particular interrupt is disabled in the interrupt enable register. 5.6.2 Clearing Subactive Mode
Subactive mode is cleared by a SLEEP instruction or by input at the RES pin. * Clearing by SLEEP instruction If a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1 and TMA3 bit in TMA is set to 1, subactive mode is cleared and watch mode is entered. If a SLEEP instruction is executed while SSBY = 0 and LSON = 1 in SYSCR1 and TMA3 = 1 in TMA, subsleep mode is entered. Direct transfer to active mode is also possible; see section 5.8, Direct Transfer, below. * Clearing by RES pin Clearing by RES pin is the same as for standby mode; see section 5.3.2, Clearing Standby Mode.
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Section 5 Power-Down Modes
5.6.3
Operating Frequency in Subactive Mode
The operating frequency in subactive mode is set in bits SA1 and SA0 in SYSCR2. The choices are W/2, W/4, and W/8.
5.7
5.7.1
Active (Medium-Speed) Mode
Transition to Active (Medium-Speed) Mode
If the MSON bit in SYSCR2 is set to 1 while the LSON bit in SYSCR1 is cleared to 0, a transition to active (medium-speed) mode results from IRQ0 or IRQ1 interrupts in standby mode, timer A or IRQ0 interrupts in watch mode, or any interrupt in sleep (medium-speed) mode. A transition to active (medium-speed) mode does not take place if the I bit of CCR is set to 1 or the particular interrupt is disabled in the interrupt enable register. 5.7.2 Clearing Active (Medium-Speed) Mode
Active (medium-speed) mode is cleared by a SLEEP instruction or by input at the RES pin. * Clearing by SLEEP instruction A transition to standby mode takes place if the SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, and the TMA3 bit in TMA is cleared to 0. The system goes to watch mode if the SSBY bit in SYSCR1 is set to 1 and bit TMA3 in TMA is set to 1 when a SLEEP instruction is executed. When both SSBY and LSON are cleared to 0 in SYSCR1 and a SLEEP instruction is executed, sleep (high-speed) mode is entered if MSON is cleared to 0 in SYSCR2, and sleep (mediumspeed) mode is entered if MSON is set to 1. Direct transfer to active (high-speed) mode or to subactive mode is also possible. See section 5.8, Direct Transfer, below for details. * Clearing by RES pin When the RES pin goes low, the CPU enters the reset state and active (medium-speed) mode is cleared. 5.7.3 Operating Frequency in Active (Medium-Speed) Mode
Operation in active (medium-speed) mode is clocked at the frequency designated by the MA1 and MA0 bits in SYSCR1.
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Section 5 Power-Down Modes
5.8
Direct Transfer
The CPU can execute programs in three modes: active (high-speed) mode, active (medium-speed) mode, and subactive mode. A direct transfer is a transition among these three modes without the stopping of program execution. A direct transfer can be made by executing a SLEEP instruction while the DTON bit in SYSCR2 is set to 1. After the mode transition, direct transfer interrupt exception handling starts. If the direct transfer interrupt is disabled in interrupt enable register 2, a transition is made instead to sleep mode or watch mode. Note that if a direct transition is attempted while the I bit in CCR is set to 1, sleep mode or watch mode will be entered, and it will be impossible to clear the resulting mode by means of an interrupt. * Direct transfer from active (high-speed) mode to active (medium-speed) mode When a SLEEP instruction is executed in active (high-speed) mode while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is set to 1, and the DTON bit in SYSCR2 is set to 1, a transition is made to active (medium-speed) mode via sleep mode. * Direct transfer from active (medium-speed) mode to active (high-speed) mode When a SLEEP instruction is executed in active (medium-speed) mode while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is cleared to 0, and the DTON bit in SYSCR2 is set to 1, a transition is made to active (high-speed) mode via sleep mode. * Direct transfer from active (high-speed) mode to subactive mode When a SLEEP instruction is executed in active (high-speed) mode while the SSBY and LSON bits in SYSCR1 are set to 1, the DTON bit in SYSCR2 is set to 1, and the TMA3 bit in TMA is set to 1, a transition is made to subactive mode via watch mode. * Direct transfer from subactive mode to active (high-speed) mode When a SLEEP instruction is executed in subactive mode while the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, the MSON bit in SYSCR2 is cleared to 0, the DTON bit in SYSCR2 is set to 1, and the TMA3 bit in TMA is set to 1, a transition is made directly to active (high-speed) mode via watch mode after the waiting time set in SYSCR1 bits STS2 to STS0 has elapsed. * Direct transfer from active (medium-speed) mode to subactive mode When a SLEEP instruction is executed in active (medium-speed) while the SSBY and LSON bits in SYSCR1 are set to 1, the DTON bit in SYSCR2 is set to 1, and the TMA3 bit in TMA is set to 1, a transition is made to subactive mode via watch mode.
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Section 5 Power-Down Modes
* Direct transfer from subactive mode to active (medium-speed) mode When a SLEEP instruction is executed in subactive mode while the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, the MSON bit in SYSCR2 is set to 1, the DTON bit in SYSCR2 is set to 1, and the TMA3 bit in TMA is set to 1, a transition is made directly to active (medium-speed) mode via watch mode after the waiting time set in SYSCR1 bits STS2 to STS0 has elapsed.
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Section 5 Power-Down Modes
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Section 6 ROM
Section 6 ROM
6.1 Overview
The H8/3644 has 32 kbytes of on-chip mask ROM, PROM or flash memory. The H8/3643 has 24 kbytes of mask ROM or flash memory. The H8/3642 has 16 kbytes of mask ROM or flash memory. The H8/3641 has 12 kbytes of on-chip ROM. H8/3640 has 8 kbytes of ROM. The ROM is connected to the CPU by a 16-bit data bus, allowing high-speed two-state access for both byte data and word data. In the PROM version (H8/3644 ZTAT) and flash memory versions (H8/3644 F-ZTAT, H8/3643 F-ZTAT, H8/3642 AF-ZTAT), programs can be written and erased with a general-purpose PROM programmer. In the on-chip flash memory versions, programs can be written and erased on-board. 6.1.1 Block Diagram
Figure 6.1 shows a block diagram of the on-chip ROM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'0000 H'0002
H'0000 H'0002
H'0001 H'0003
On-chip ROM H'7FFE H'7FFE Even-numbered address H'7FFF Odd-numbered address
Figure 6.1 ROM Block Diagram (H8/3644)
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Section 6 ROM
6.2
6.2.1
PROM Mode
Setting to PROM Mode
If the on-chip ROM is PROM, setting the chip to PROM mode stops operation as a microcontroller and allows the PROM to be programmed in the same way as the standard HN27C256 EPROM. Table 6.1 shows how to set the chip to PROM mode. Table 6.1
Pin Name TEST PB4/AN4 PB5/AN5 PB6/AN6 High level
Setting to PROM Mode
Setting High level Low level
6.2.2
Memory Map
Figure 6.2 shows a memory map.
Address in MCU mode H'0000
Address in PROM mode H'0000
On-chip PROM
H'7FFF
H'7FFF
Figure 6.2 H8/3644 Memory Map in PROM Mode When programming with a PROM programmer, be sure to specify addresses from H'0000 to H'7FFF.
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Section 6 ROM
6.3
Programming
The H8/3644 write, verify, and other modes are selected as shown in table 6.2 in PROM mode. Table 6.2 Mode Selection in PROM Mode (H8/3644)
Pin Mode Write Verify Programming disabled Legend: L: Low level H: High level VPP: VPP level VCC: VCC level CE L H H OE H L H VPP VPP VPP VPP VCC VCC VCC VCC EO7 to EO0 Data input Data output High impedance EA14 to EA0 Address input Address input Address input
The specifications for writing and reading are identical to those for the standard HN27C256 EPROM.
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Section 6 ROM
6.3.1
Writing and Verifying
An efficient, high-speed, high-reliability method is available for writing and verifying the PROM data. This method achieves high speed without voltage stress on the device and without lowering the reliability of written data. Data in unused address areas has a value of H'FF. The basic flow of this high-speed, high-reliability programming method is shown in figure 6.3.
Start
Set write/verify mode VCC = 6.0 V 0.25 V, VPP = 12.5 V 0.3 V Address = 0 n=0 n+1 n No Yes n < 25 NG Write time tPW = 0.2 ms 5%
Verify OK Write time tOPW = 3n ms No
Address + 1 address
Last address? Yes
Set read mode VCC = 5.0 V 0.5 V, VPP = VCC NG
Error
Read all addresses? Yes End
Figure 6.3 High-Speed, High-Reliability Programming Flow Chart
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Section 6 ROM
Table 6.3 and table 6.4 give the electrical characteristics in programming mode. Table 6.3 DC Characteristics
(Conditions: VCC = 6.0 V 0.25 V, VPP = 12.5 V 0.3 V, VSS = 0 V, Ta = 25C 5C)
Item Input highlevel voltage Input lowlevel voltage Output highlevel voltage Output lowlevel voltage Symbol EO7 to EO0, EA14 to EA0 VIH OE, CE EO7 to EO0, EA14 to EA0 VIL OE, CE EO7 to EO0 EO7 to EO0 VOH VOL Min 2.4 -0.3 2.4 Typ Max VCC +0.3 0.8 0.45 2 40 40 Unit V V V V A mA mA IOH = -200 A IOL = 0.8 mA Vin = 5.25 V/ 0.5 V Test Condition
Input leakage EO7 to EO0, EA14 to EA0 |ILI| current OE, CE VCC current VPP current ICC IPP
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Section 6 ROM
Table 6.4
AC Characteristics
(Conditions: VCC = 6.0 V 0.25 V, VPP = 12.5 V 0.3 V, Ta = 25C 5C)
Item Address setup time OE setup time Data setup time Address hold time Data hold time Data output disable time VPP setup time Programming pulse width CE pulse width for overwrite programming VCC setup time Data output delay time Symbol tAS tOES tDS tAH tDH 2 tDF* tVPS tPW
3 tOPW *
Min 2 2 2 0 2 0 2 0.95 2.85 2 0
Typ 1.0
Max 130 1.05 78.7 500
Unit s s s s s ns s ms ms s ns
Test Condition Figure 6.4*
1
tVCS tOE
Notes: 1. Input pulse level: 0.8 V to 2.2 V Input rise time/fall time 20 ns Timing reference levels: Input: 1.0 V, 2.0 V Output: 0.8 V, 2.0 V 2. tDF is defined at the point at which the output is floating and the output level cannot be read. 3. tOPW is defined by the value given in figure 6.3, High-Speed, High-Reliability Programming Flow Chart.
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Section 6 ROM
Figure 6.4 shows a PROM write/verify timing diagram.
Write Address tAS Data tDS VPP VPP VCC VCC+1 VCC tVCS tVPS Input data tDH tAH Output data tDF Verify
VCC
CE tPW OE tOPW* tOES tOE
Note: * tOPW is defined by the value given in figure 6.3, High-Speed, High-Reliability Programming Flow Chart.
Figure 6.4 PROM Write/Verify Timing 6.3.2 Programming Precautions
* Use the specified programming voltage and timing. The programming voltage in PROM mode (VPP) is 12.5 V. Use of a higher voltage can permanently damage the chip. Be especially careful with respect to PROM programmer overshoot. Setting the PROM programmer to Renesas Technology specifications for the HN27C256 will result in correct VPP of 12.5 V. * Make sure the index marks on the PROM programmer socket, socket adapter, and chip are properly aligned. If they are not, the chip may be destroyed by excessive current flow. Before programming, be sure that the chip is properly mounted in the PROM programmer.
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Section 6 ROM
* Avoid touching the socket adapter or chip while programming, since this may cause contact faults and write errors. 6.3.3 Reliability of Programmed Data
A highly effective way to improve data retention characteristics is to bake the programmed chips at 150C, then screen them for data errors. This procedure quickly eliminates chips with PROM memory cells prone to early failure. Figure 6.5 shows the recommended screening procedure.
Program chip and verify programmed data
Bake chip for 24 to 48 hours at 125 C to 150 C with power off
Read and check program
Install
Figure 6.5 Recommended Screening Procedure If a group of programming errors occurs while the same PROM programmer is in use, stop programming and check the PROM programmer and socket adapter for defects, using a microcomputer with on-chip EPROM in a windowed package, etc. Please inform Renesas Technology of any abnormal conditions noted during or after programming or in screening of program data after high-temperature baking.
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Section 6 ROM
6.4
6.4.1
Flash Memory Overview
Principle of Flash Memory Operation
Table 6.5 illustrates the principle of operation of the on-chip flash memory in the H8/3644F, H8/3643F, and H8/3642AF. Like EPROM, flash memory is programmed by applying a high gate-to-drain voltage that draws hot electrons generated in the vicinity of the drain into a floating gate. The threshold voltage of a programmed memory cell is therefore higher than that of an erased cell. Cells are erased by grounding the gate and applying a high voltage to the source, causing the electrons stored in the floating gate to tunnel out. After erasure, the threshold voltage drops. A memory cell is read like an EPROM cell, by driving the gate to a high level and detecting the drain current, which depends on the threshold voltage. Erasing must be done carefully, because if a memory cell is overerased, its threshold voltage may become negative, causing the cell to operate incorrectly. Section 6.7.6, Erase Flowcharts and Sample Programs, shows optimal erase control flowcharts and sample programs. Table 6.5 Principle of Memory Cell Operation
Program Memory cell
Vg = VPP Vd
Erase
Read
Vg = VCC Vd
Vs = VPP
Open
Memory array
Vd
0V VPP 0V 0V
Open
Open 0V VPP 0V
Vd
0V VCC 0V 0V
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Section 6 ROM
6.4.2
Mode Pin Settings and ROM Space
The H8/3644F has 32 kbytes of on-chip flash memory, the H8/3643F has 24 kbytes, and the H8/3642AF has 16 kbytes. The ROM is connected to the CPU by a 16-bit data bus. The CPU accesses flash memory in two states for both byte-size and word-size instructions. The flash memory is allocated to addresses H'0000 to H'7FFF in the H8/3644F, to addresses H'0000 to H'5FFF in the H8/3643F, and to addresses H'0000 to H'3FFF in the H8/3642AF. 6.4.3 Features
The features of the flash memory are summarized below. * Five flash memory operating modes There are five flash memory operating modes: program mode, program-verify mode, erase mode, erase-verify mode, and prewrite-verify mode. * Erase block specification Blocks to be erased in the flash memory space can be specified by setting the corresponding register bits. The address space includes a large block area (four blocks with sizes from 4 kbytes to 8 kbytes) and a small block area (eight blocks with sizes from 128 bytes to 1 kbyte). * Programming/erase times The flash memory programming time is 50 s (typ.) per byte, and the erase time is 1 s (typ.). * Erase-program cycles Flash memory contents can be erased and reprogrammed up to 100 times. * On-board programming modes There are two modes in which flash memory can be programmed, erased, and verified onboard: boot mode and user program mode. * Automatic bit rate adjustment For data transfer in boot mode, the chip's bit rate can be automatically adjusted to match the transfer bit rate of the host (max. 9600 bps). * PROM mode Flash memory can be programmed and erased in PROM mode, using a general-purpose PROM programmer, as well as in on-board programming mode. The specifications for programming, erasing, verifying, etc., are the same as for standard HN28F101 flash memory.
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Section 6 ROM
6.4.4
Block Diagram
Figure 6.6 shows a block diagram of the flash memory.
8 Internal data bus (upper) 8 Internal data bus (lower)
FLMCR EBR1
Bus interface/control section
Operating mode
TEST
H'0000 EBR2 H'0002 H'0004
H'0001 H'0003 H'0005
On-chip flash memory (32 kbytes) H'7FFC H'7FFE Upper byte (even address) Legend: FLMCR: Flash memory control register EBR1: Erase block register 1 EBR2: Erase block register 2 H'7FFD H'7FFF Lower byte (odd address)
Figure 6.6 Block Diagram of Flash Memory (Example of the H8/3644F)
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Section 6 ROM
6.4.5
Pin Configuration
The flash memory is controlled by means of the pins shown in table 6.6. Table 6.6
Pin Name Programming power Mode pin Transmit data Receive data
Flash Memory Pins
Abbreviation FVPP TEST TXD RXD Input/Output Power supply Input Output Input Function Apply 12.0 V Sets H8/3644F operating mode SCI3 transmit data output SCI3 receive data input
The transmit data pin and receive data pin are used in boot mode. 6.4.6 Register Configuration
The registers used to control the on-chip flash memory are shown in table 6.7. Table 6.7 Flash Memory Registers
Abbreviation FLMCR EBR1 EBR2 R/W R/W R/W R/W Initial Value H'00 H'F0 H'00 Address H'FF80 H'FF82 H'FF83
Register Name Flash memory control register Erase block register 1 Erase block register 2
The FLMCR, EBR1, and EBR2 registers are valid only when programming and erasing flash memory, and can only be accessed when 12 V is applied to the FVPP pin. When 12 V is not applied to the FVPP pin, addresses H'FF80 to H'FF83 cannot be modified and are always read as H'FF.
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Section 6 ROM
6.5
6.5.1
Flash Memory Register Descriptions
Flash Memory Control Register (FLMCR)
FLMCR is an 8-bit register used for flash memory operating mode control. Transitions to program mode, erase mode, program-verify mode, and erase-verify mode are made by setting bits in this register. FLMCR is initialized to H'00 upon reset, in sleep mode, subsleep mode, watch mode, and standby mode, and when 12 V is not applied to FVPP. When 12 V is applied to FVPP, a reset initializes FLMCR to H'80.
Bit Initial value Read/Write Note: * 7 VPP 0 R 6 0 5 0 4 0 3 EV 0 R/W * 2 PV 0 R/W * 1 E 0 R/W * 0 P 0 R/W *
For information on access to this register, see note 11 in section 6.9, Flash Memory Programming and Erasing Precautions.
Bit 7Programming Power (VPP): Bit 7 is a status flag that indicates that 12 V is applied to the FVPP pin. For further information, see note 5 in section 6.9, Flash Memory Programming and Erasing Precautions.
Bit 7: VPP 0 1 Description Clearing condition: When 12 V is not applied to the FVPP pin Setting condition: When 12 V is applied to the FVPP pin (initial value)
Bit 3Erase-Verify Mode (EV)*: Bit 3 selects transition to or exit from erase-verify mode.
Bit 3: EV 0 1 Note: * Description Exit from erase-verify mode Transition to erase-verify mode Do not set multiple bits simultaneously. Do not release or cut the VCC or VPP power supply while a bit is set. (initial value)
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Section 6 ROM
Bit 2Program-Verify Mode (PV)*: Bit 2 selects transition to or exit from program-verify mode.
Bit 2: PV 0 1 Note: * Description Exit from program-verify mode Transition to program-verify mode Do not set multiple bits simultaneously. Do not release or cut the VCC or VPP power supply while a bit is set. (initial value)
Bit 1Erase Mode (E)*1*2: Bit 1 selects transition to or exit from erase mode.
Bit 1: E 0 1 Description Exit from erase mode Transition to erase mode (initial value)
Notes: 1. Do not set multiple bits simultaneously. Do not release or cut the VCC or VPP power supply while a bit is set. 2. P bit and E bit setting should be carried out in accordance with the program/erase algorithms shown in section 6.7, Programming and Erasing Flash Memory. A watchdog timer setting should be made beforehand to prevent the P or E bit from being set for longer than the specified time. See section 6.9, Flash Memory Programming and Erasing Precautions, for more information on the use of these bits.
Bit 0Program Mode (P)*1*2: Bit 0 selects transition to or exit from program mode.
Bit 0: P 0 1 Description Exit from program mode Transition to program mode (initial value)
Notes: 1. Do not set multiple bits simultaneously. Do not release or cut the VCC or VPP power supply while a bit is set. 2. P bit and E bit setting should be carried out in accordance with the program/erase algorithms shown in section 6.7, Programming and Erasing Flash Memory. A watchdog timer setting should be made beforehand to prevent the P or E bit from being set for longer than the specified time. See section 6.9, Flash Memory Programming and Erasing Precautions, for more information on the use of these bits.
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Section 6 ROM
6.5.2
Erase Block Register 1 (EBR1)
EBR1 is an 8-bit register that specifies large flash-memory blocks for programming or erasure. EBR1 is initialized to H'F0 upon reset, in sleep mode, subsleep mode, watch mode, and standby mode, and when 12 V is not applied to FVPP. When a bit in EBR1 is set to 1, the corresponding block is selected and can be programmed and erased. The erase block map is shown in figure 6.7, and the correspondence between bits and erase blocks is shown in table 6.8.
Bit Initial value Read/Write Note: * 7 1 6 1 5 1 4 1 3 LB3 0 R/W * 2 LB2 0 R/W * 1 LB1 0 R/W * 0 LB0 0 R/W *
Word access cannot be used on this register; byte access must be used. For information on access to this register, see note 11 in section 6.9, Flash Memory Programming and Erasing Precautions. LB3 is invalid in the H8/3643F, and LB3 and LB2 are invalid in the H8/3642AF.
Bits 7 to 4Reserved: Bits 7 to 4 are reserved; they are always read as 1, and cannot be modified. Bits 3 to 0Large Block 3 to 0 (LB3 to LB0): These bits select large blocks (LB3 to LB0) to be programmed and erased.
Bits 3 to 0: LB3 to LB0 0 1 Description Block LB3 to LB0 is not selected Block LB3 to LB0 is selected (initial value)
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Section 6 ROM
6.5.3
Erase Block Register 2 (EBR2)
EBR2 is an 8-bit register that specifies small flash-memory blocks for programming or erasure. EBR2 is initialized to H'00 upon reset, in sleep mode, subsleep mode, watch mode, and standby mode, and when 12 V is not applied to FVPP. When a bit in EBR2 is set to 1, the corresponding block is selected and can be programmed and erased. The erase block map is shown in figure 6.7, and the correspondence between bits and erase blocks is shown in table 6.8.
Bit Initial value Read/Write Note: * 7 SB7 0 R/W * 6 SB6 0 R/W * 5 SB5 0 R/W * 4 SB4 0 R/W * 3 SB3 0 R/W * 2 SB2 0 R/W * 1 SB1 0 R/W * 0 SB0 0 R/W *
Word access cannot be used on this register; byte access must be used. For information on access to this register, see note 11 in section 6.9, Flash Memory Programming and Erasing Precautions. LB3 is invalid in the H8/3643F, and LB3 and LB2 are invalid in the H8/3642AF.
Bits 7 to 0Small Block 7 to 0 (SB7 to SB0): These bits select small blocks (SB7 to SB0) to be programmed and erased.
Bits 7 to 0: SB7 to SB0 0 1 Description Block SB7 to SB0 is not selected Block SB7 to SB0 is selected (initial value)
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Section 6 ROM
H'0000 SB7 to SB0 (4 kbytes) H'0FFF H'1000 LB0 (4 kbytes) H'1FFF H'2000 (H8/3642AF: 12 kbytes) LB1 (8 kbytes) H'3FFF H'4000 (H8/3643F: 20 kbytes) LB2 (8 kbytes) H'5FFF H'6000 LB3 (8 kbytes) H'7FFF H'0FFF H'0BFF H'0C00 SB7 (1 kbyte) H'07FF H'0800 SB6 (1 kbyte) H'03FF H'0400 SB5 (1 kbyte) H'0000
Small block area (4 kbytes) Large block area (H8/3644F: 28 kbytes)
SB0 SB1 SB2 H'01FF SB3 H'0200
(128 bytes) (128 bytes) (128 bytes) (128 bytes)
SB4 (512 bytes)
Figure 6.7 Erase Block Map Table 6.8
Register EBR1
Correspondence between Erase Blocks and EBR1/EBR2 Bits
Bit 0 1 2 3 Block LB0 LB1 LB2 LB3 Block SB0 SB1 SB2 SB3 SB4 SB5 SB6 SB7 Addresses H'1000 to H'1FFF H'2000 to H'3FFF H'4000 to H'5FFF H'6000 to H'7FFF Addresses H'0000 to H'007F H'0080 to H'00FF H'0100 to H'017F H'0180 to H'01FF H'0200 to H'03FF H'0400 to H'07FF H'0800 to H'0BFF H'0C00 to H'0FFF Size 4 kbytes 8 kbytes 8 kbytes 8 kbytes Size 128 bytes 128 bytes 128 bytes 128 bytes 512 bytes 1 kbyte 1 kbyte 1 kbyte
Register EBR2
Bit 0 1 2 3 4 5 6 7
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Section 6 ROM
6.6
On-Board Programming Modes
When an on-board programming mode is selected, on-chip flash memory programming, erasing, and verifying can be carried out. There are two on-board programming modesboot mode and user program modeset by the mode pin (TEST) and the FVPP pin. Table 6.9 shows how to select the on-board programming modes. For information on turning VPP on and off, see note 5 in section 6.9, Flash Memory Programming and Erasing Precautions. Table 6.9 On-Board Programming Mode Selection
FVPP 12 V* TEST 12 V* VSS Notes
Mode Setting Boot mode User program mode Note: *
See notes 6 to 8 in section 6.6.1, Notes on Use of Boot Mode, for the timing of 12 V application.
6.6.1
Boot Mode
When boot mode is used, a user program for flash memory programming and erasing must be prepared beforehand in the host machine (which may be a personal computer). SCI3 is used in asynchronous mode (see figure 6.8). When the H8/3644F, H8/3643F, or H8/3642AF is set to boot mode, after reset release a built-in boot program is activated, the low period of the data sent from the host is first measured, and the bit rate register (BRR) value determined. The chip's on-chip serial communication interface (SCI3) can then be used to download the user program from the host machine. The downloaded user program is written into RAM. After the program has been stored, execution branches to the start address (H'FBE0) of the on-chip RAM, the program stored in RAM is executed, and flash memory programming/erasing can be carried out. Figure 6.9 shows the boot mode execution procedure.
Reception of programming data HOST Transmission of verify data
H8/3644F, H8/3643F, or H8/3642AF RXD SCI3 TXD
Figure 6.8 Boot Mode System Configuration
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Section 6 ROM
Boot Mode Execution Procedure: The boot mode execution procedure is shown below.
Start 1 Set pins to boot mode for chip and execute reset-start Host transmits H'00 data continuously at prescribed bit rate Chip measures low period of H'00 data transmitted by host 3 Chip calculates bit rate and sets value in bit rate register After bit rate adjustment, chip transmits one H'00 data byte to host to indicate end of adjustment Host confirms normal reception of bit rate adjustment end indication, and transmits one H'55 data byte After receiving H'55, chip transfers part of boot program to RAM Chip branches to RAM boot area (H'FC00 to H'FF2F), then checks flash memory user area data All data = H'FF? YES No Erase all flash memory blocks*3 1. Set the chip to boot mode and execute a reset-start. 2. Set the host to the prescribed bit rate (2400/4800/9600) and have it transmit H'00 data continuously using a transfer data format of 8-bit data plus 1 stop bit. 3. The chip repeatedly measures the low period at the RXD pin and calculates the asynchronous communication bit rate used by the host. 4. After SCI3 bit rate adjustment is completed, the chip transmits one H'00 data byte to indicate the end of adjustment. 5. On receiving the one-byte data indicating completion of bit rate adjustment, the host should confirm normal reception of this indication and transmit one H'55 data byte. 6. After receiving H'55, the chip transfers part of the boot program to RAM areas H'FB80 to H'FBDF and H'FC00 to H'FF2F. 7. The chip branches to the RAM boot program area (H'FC00-H'FF2F) and checks for the presence of data written in the flash memory. If data has been written in the flash memory, the chip erases all blocks. 8. The chip transmits one H'AA byte. The host then transmits the number of user program bytes to be transferred to the chip. The number of bytes should be sent as two bytes, upper byte followed by lower byte. The host should then transmit sequentially the program set by the user. The chip transmits the received byte count and user program sequentially to the host, one byte at a time, as verify data (echo-back). 9. The chip writes the received user program sequentially to on-chip RAM area H'FBE0 to H'FF6D (910 bytes). 10. The chip transmits one H'AA byte, then branches to onchip RAM address H'FBE0 and executes the user program written in area H'FBE0 to H'FF6D. Notes: 1. The size of the RAM area available to the user is 910 bytes. The number of bytes to be transferred must not exceed 910 bytes. The transfer byte count must be sent as two bytes, upper byte followed by lower byte. Example of transfer byte count: for 256 bytes (H'0100), upper byte = H'01, lower byte = H'00 2. The part of the user program that controls the flash memory should be set in the program in accordance with the flash memory program/ erase algorithms described later in this section. 3. If a memory cell does not operate normally and cannot be erased, the chip transmits one H'FF byte as an erase error indication and halts the erase operation and subsequent operations.
2
4
5
6
7
After confirming that all flash memory data is H'FF, chip transmits one H'AA byte to host 8 Chip receives, as 2 bytes, number of program bytes (N) to be transferred to on-chip RAM*1
Chip transfers user program to RAM*2 Chip calculates remaining bytes to be transferred (N = N - 1)*2 Transfer No end byte count N = 0? Yes Chip transfers user program to RAM, then transmits one H'AA byte to host 10 Chip branches to RAM area address H'FBE0 and executes user program transferred to RAM
9
Figure 6.9 Boot Mode Operation Flowchart
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Section 6 ROM
Automatic SCI Bit Rate Adjustment: When boot mode is initiated, the H8/3644F, H8/3643F, or H8/3642AF measures the low period of the asynchronous SCI communication data transmitted continuously from the host (figure 6.10). The data format should be set as 8-bit data, 1 stop bit, no parity. The chip calculates the bit rate of the transmission from the host from the measured low period (9 bits), and transmits one H'00 byte to the host to indicate the end of bit rate adjustment. The host should confirm that this adjustment end indication has been received normally, and transmit one H'55 byte to the chip. If reception cannot be performed normally, initiate boot mode again (reset), and repeat the above operations. Depending on the host's transmission bit rate and the chip's system clock oscillation frequency (fOSC), there will be a discrepancy between the bit rates of the host and the chip. To insure correct SCI operation, the host's transfer bit rate should be set to 2400, 4800, or 9600 bps*1. Table 6.10 shows typical host transfer bit rates and system clock oscillation frequency for which automatic adjustment of the chip's bit rate is possible. Boot mode should be used within this system clock oscillation frequency range*2. Notes: 1. Only use a host bit rate setting of 2400, 4800, or 9600 bps. No other bit rate setting should be used. 2. Although the chip may also perform automatic bit rate adjustment with bit rate and system clock oscillation frequency combinations other than those shown in table 6.10, a degree of error will arise between the bit rates of the host and the chip, and subsequent transfer will not be performed normally. Therefore, only a combination of bit rate and system clock oscillation frequency within one of the ranges shown in table 6.10 can be used for boot mode execution.
Start bit
D0
D1
D2
D3
D4
D5
D6
D7
Stop bit
Low period (9 bits) measured (H'00 data) High period (1 or more bits)
Figure 6.10 Measurement of Low Period in Transmit Data from Host
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Section 6 ROM
Table 6.10 System Clock Oscillation Frequencies Permitting Automatic Adjustment of Chip (H8/3644F, H8/3643F, H8/3642AF) Bit Rate
Host Bit Rate* 9600 bps 4800 bps 2400 bps Note: * System Clock Oscillation Frequencies (fOSC) Permitting Automatic Adjustment of Chip (H8/3644F, H8/3643F, H8/3642AF) Bit Rate 8 MHz to 16 MHz 4 MHz to 16 MHz 2 MHz to 16 MHz Use a host bit rate setting of 2400, 4800, or 9600 bps only. No other setting should be used.
RAM Area Allocation in Boot Mode: In boot mode, the 96-byte area from H'FB80 to H'FBDF and the 18-byte area from H'FF6E to H'FF7F are reserved for boot program use, as shown in figure 6.11. The area to which the user program is transferred is H'FBE0 to H'FF6D (910 bytes). The boot program area becomes available when a transition is made to the execution state for the user program transferred to RAM. A stack area should be set within the user program as required.
H'FB80
Boot program area* (96 bytes)
H'FBE0
User program transfer area (910 bytes)
H'FF6E H'FF7F
Boot program area* (18 bytes)
Note: * These areas cannot be used until a transition is made to the execution state for the user program transferred to RAM (i.e. a branch is made to RAM address H'FBE0). Note also that the boot program remains in the boot program area in RAM (H'FB80 to H'FBDF, H'FF6E to H'FF7F) even after control branches to the user program. When an interrupt handling routine is executed in the boot program, the 16 bytes from H'FB80 to H'FB8F in this area cannot be used. For details see section 6.7.9, Interrupt Handling during Flash Memory Programming/Erasing.
Figure 6.11 RAM Areas in Boot Mode
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Section 6 ROM
Notes on Use of Boot Mode: 1. When the chip (H8/3644F, H8/3643F, or H8/3642AF) comes out of reset in boot mode, it measures the low period of the input at the SCI3's RXD pin. The reset should end with RXD high. After the reset ends, it takes about 100 states for the chip to get ready to measure the low period of the RXD input. 2. In boot mode, if any data has been programmed into the flash memory (if all data is not H'FF), all flash memory blocks are erased. Boot mode is for use when user program mode is unavailable, such as the first time on-board programming is performed, or if the program activated in user program mode is accidentally erased. 3. Interrupts cannot be used while the flash memory is being programmed or erased. 4. The RXD and TXD lines should be pulled up on the board. 5. Before branching to the user program (RAM address H'FBE0), the chip terminates transmit and receive operations by its on-chip SCI3 (by clearing the RE and TE bits to 0 in the serial control register (SCR)), but the adjusted bit rate value remains set in the bit rate register (BRR). The transmit data output pin, TXD, goes to the high-level output state (PCR22 = 1 in the port 2 control register, P22 = 1 in the port 2 data register). The contents of the CPU's internal general registers are undefined at this time, so these registers must be initialized immediately after branching to the user program. In particular, since the stack pointer (SP) is used implicitly in subroutine calls, etc., a stack area must be specified for use by the user program. The initial values of other on-chip registers are not changed. 6. Boot mode can be entered by applying 12 V to the TEST pin and FVPP pin in accordance with the mode setting conditions shown in table 6.9, and then executing a reset-start. Care must be taken with turn-on of the VPP power supply at this time. On reset release (a low-to-high transition), the chip determines whether 12 V is being applied to the TEST pin and FVPP pin, and on detecting that boot mode has been set, retains that state internally. As the applied voltage criterion level (threshold level) at this time is the range of approximately VCC +2 V to 11.4 V, a transition will be made to boot mode even if a voltage sufficient for executing programming and erasing (11.4 V to 12.6 V) is not being applied. Therefore, when executing the boot program, the VPP power supply must be stabilized within the range of 11.4 V to 12.6 V before a branch is made to the RAM area, as shown in figure 6.22. Insure that the program voltage VPP does not exceed 12.6 V when a transition is made to boot mode (when reset is released), and does not exceed the range 12 V 0.6 V during boot mode operation. If these values are exceeded, boot mode execution will not be performed correctly. Also, do not release or cut VPP during boot mode execution or when programming or erasing flash memory*.
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Section 6 ROM
Boot mode can be exited by driving the reset pin low, then releasing 12 V application to the TEST pin and FVPP pin at least 10 system clock cycles later, and setting the TEST pin to VSS to release the reset. However, external pin settings must not be changed during boot mode execution. Note that the boot mode state is not maintained if 12 V application to the TEST pin is released while in boot mode. Also, if a watchdog timer reset occurs in this boot mode state, the built-in boot program will be restarted without clearing the MCU's internal mode state. 7. If the TEST pin input level is changed (e.g. from 0 V to 5 V to 12 V) during a reset (while a low level is being input at the RES pin), port states will change as a result of the change of MCU operating mode. Therefore, care must be taken to make pin settings to prevent these pins from becoming output signal pins during a reset, and to prevent collision with signals outside the MCU. 8. Regarding 12 V application to the FVPP and TEST pins, insure that peak overshoot does not exceed the maximum rating of 13 V. Also, be sure to connect bypass capacitors to the FVPP and TEST pins. Note: * For further information on VPP application, release, and cut-off, see note 5 in section 6.9, Flash Memory Programming and Erasing Precautions. 6.6.2 User Program Mode
When set to user program mode, the H8/3644F, H8/3643F, or H8/3642AF can program and erase its flash memory by executing a user program. Therefore, on-board reprogramming of the on-chip flash memory can be carried out by providing on-board means of supplying VPP and programming data, and storing an on-board reprogramming program in part of the program area. User program mode is selected by applying 12 V to the FVPP pin when flash memory is not being accessed, during a reset or after confirming that a reset has been performed properly (after the reset is released). The flash memory cannot be read while being programmed or erased, so the on-board reprogramming program or flash memory reprogramming routine should be transferred to the RAM area, and on-board reprogramming executed in that area.
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Section 6 ROM
User Program Mode Execution Procedure*1: The procedure for user program execution in RAM is shown below.
1
Reset-start (TEST = VSS)
Procedure: An on-board reprogramming program must be written into flash memory by the user beforehand. 1. Set the TEST pin to VSS and execute a reset-start. 2. Branch to the on-board reprogramming program written to flash memory. 3. Transfer the flash memory reprogramming routine to the RAM area. 4. Branch to the flash memory reprogramming routine transferred to the RAM area. 5. Apply 12 V to the FVPP pin. (Transition to user program mode)
2
Branch to flash memory on-board reprogramming program
3
Transfer flash memory reprogramming routine to RAM
4
Branch to flash memory reprogramming routine in RAM area
5
FVPP = 12 V (user program mode)
6. Execute the flash memory reprogramming routine in the RAM area, an perform on-board reprogramming of the flash memory. 7. Switch the FVPP pin from 12 V to VCC, and exit user program mode. 8. After on-board reprogramming of the flash memory ends, branch to the flash memory application program.
6
Execute flash memory reprogramming routine in RAM area (flash memory reprogramming)
7
Release FVPP (exit user program mode)
8
Branch to flash memory application program*2
Notes: 1. Do not apply 12 V to the FVPP pin during normal operation. To prevent inadvertent programming or erasing due to program runaway, etc., apply 12 V to the FVPP pin only when the flash memory is being programmed or erased . Memory cells may not operate normally if overprogrammed or overerased due to program runaway, etc. Also, while 12 V is applied to the FVPP pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. For further information on FVPP application, release, and cut-off, see note 5 in section 6.9, Flash Memory Programming and Erasing Precautions. 2. When the application of 12 V to the FVPP pin is released after programming is completed, the flash memory read setup time (tFRS) must elapse before executing a program in flash memory. This specifies the setup time from the point at which the FVPP voltage reaches the VCC + 2 V level after 12 V application is released until the flash memory is read.
Figure 6.12 Example of User Program Mode Operation
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Section 6 ROM
6.7
Programming and Erasing Flash Memory
The on-chip flash memory of the H8/3644F, H8/3643F, and H8/3642AF is programmed and erased by software, using the CPU. There are five flash memory operating modes: program mode, erase mode, program-verify mode, erase-verify mode, and prewrite-verify mode. Transitions to these modes can be made by setting the P, E, PV, and EV bits in the flash memory control register (FLMCR). The flash memory cannot be read while being programmed or erased. Therefore, the program that controls flash memory programming and erasing should be located and executed in on-chip RAM or external memory. A description of each mode is given below, with recommended flowcharts and sample programs for programming and erasing. See section 6.9, Flash Memory Programming and Erasing Precautions, for additional notes on programming and erasing. 6.7.1 Program Mode
To write data into the flash memory, follow the programming algorithm shown in figure 6.13. This programming algorithm enables data to be written without subjecting the device to voltage stress or impairing the reliability of the programmed data. To write data, first set the blocks to be programmed with erase block registers 1 and 2 (EBR1, EBR2), and write the data to the address to be programmed, as in writing to RAM. The flash memory latches the programming address and programming data in an address latch and data latch. Next set the P bit in FLMCR, selecting program mode. The programming time is the time during which the P bit is set. Make a setting so that the total programming time does not exceed 1 ms. Programming for too long a time, due to program runaway for example, can damage the device. Before selecting program mode, set up the watchdog timer so as to prevent overprogramming. For details of the programming procedure, see section 6.7.3, Programming Flowchart and Sample Program.
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Section 6 ROM
6.7.2
Program-Verify Mode
In program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory. After the elapse of the programming time, exit programming mode (clear the P bit to 0) and select program-verify mode (set the PV bit to 1). In program-verify mode, a program-verify voltage is applied to the memory cells at the latched address. If the flash memory is read in this state, the data at the latched address will be read. After selecting program-verify mode, wait at least 4 s before reading, then compare the programmed data with the verify data. If they agree, exit program-verify mode and program the next address. If they do not agree, select program mode again and repeat the same program and program-verify sequence. Do not repeat the program and program-verify sequence more than six times* for the same bit. Note: * When a bit is programmed repeatedly, set a loop counter so that the total programming time will not exceed 1 ms.
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Section 6 ROM
6.7.3
Programming Flowchart and Sample Program
Flowchart for Programming One Byte
Start Set erase block register (set bit for block to be programmed to 1) Write data to flash memory (flash memory latches write address and data) *1 n=1 Enable watchdog timer *2
Select program mode (P bit = 1 in FLMCR) Wait (x) s *4 Clear P bit End of programming
Disable watchdog timer Select program-verify mode (PV bit = 1 in FLMCR) Wait (tvs1) s *5 Verify *3 (read memory) OK Clear PV bit
Notes: 1. Write the data to be programmed using a byte transfer instruction. 2. For the timer overflow interval, set the timer counter value (TCW) to H'FE. 3. Read the memory data to be verified using a byte transfer instruction. 4. Programming time x is successively incremented to initial set value x 2n-1 (n = 1 to 6). The initial value should therefore be set to 15.8 s or less to make the total programming time 1 ms or less. 5. tvs1: 4 s or more N: 6 (set N so that total programming time does not exceed 1 ms)
NG
Clear PV bit
End of verify
Clear erase block register (clear bit for programmed block to 0)
n N? *5 Yes Programming error
No n+1n Double the programming time (x x 2 x)
End (1-byte data programmed)
Figure 6.13 Programming Flowchart
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Section 6 ROM
Sample Program for Programming One Byte This program uses the following registers: R0H: Used for erase block specification. R1H: Stores programming data. R1L: Stores read data. R3: R4: R5: Stores the programming address. Valid address specifications are H'0000 to H'EF7F. Used for program and program-verify loop counter value setting. Also stores register set values. Used for program loop counter value setting.
R6L: Used for the program-verify fail count. Arbitrary data can be programmed at an arbitrary address by setting the R3 (programming address) and R1H (programming data) values. The values of #a and #b depend on the operating frequency. They should be set as indicated in table 6.11.
FLMCR: .EQU EBR1: EBR2: .EQU .EQU H'FF80 H'FF82 H'FF83 H'FFBE H'FFBF
TCSRW: .EQU TCW: .EQU
.ALIGN 2 PRGM: MOV.B MOV.B #H'**, R0H R0H, @EBR*:8 ; ;Set EBR* ; Program-verify fail count ; Set program loop counter ; Dummy write ; Program-verify fail counter + 1 R6L #H'FE5A, R4 R4L, R4H, ; @TCSRW:8 ; @TCW:8 ; ; ; Set program loop counter
MOV.B MOV.W MOV.B PRGMS: INC R6L MOV.W MOV.B MOV.B MOV.B MOV.B MOV.W
#H'00, R6L #H'a, R1H, R5 @R3
#H'36, R4L R4L, R5,
@TCSRW:8 ; Start watchdog timer R4
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Section 6 ROM BSET LOOP1: SUBS MOV.W BNE BCLR MOV.B MOV.B #0, #1, R4, LOOP1 #0, #H'50, R4L, @FLMCR:8 ; Set P bit R4 R4 ; ; ; Wait loop @FLMCR:8 ; Clear P bit R4L ; @TCSRW:8 ; Stop watchdog timer ;Set program-verify fail counter @FLMCR:8 ; Set PV bit ; ; Wait loop R1L R1L ; Read programmed data ; Compare programmed data with read data ; Program-verify decision @FLMCR:8 ; Clear PV bit ; Program-verify executed 6 times? ; If program-verify executed 6 times, branch to NGEND R5 ; Double programming time ; Program again ; Clear PV bit ;
MOV.B BSET LOOP2: DEC BNE MOV.B CMP.B BEQ BCLR
#H'b, #2, R4H LOOP2 @R3, R1H, PVOK #2,
R4H
CMP.B BEQ ADD.W BRA
#H'06, NGEND R5, PRGMS
R6L
PVOK:
BCLR MOV.B MOV.B
#2, #H'00, R6L,
@FLMCR:8 R6L
@EBR*:8 ; Clear EBR*
One byte programmed
NGEND: Programming error
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Section 6 ROM
6.7.4
Erase Mode
To erase the flash memory, follow the erasing algorithm shown in figure 6.14. This erasing algorithm enables data to be erased without subjecting the device to voltage stress or impairing the reliability of the programmed data. To erase flash memory, before starting to erase, first place all memory data in all blocks to be erased in the programmed state (program all memory data to H'00). If all memory data is not in the programmed state, follow the sequence described later to program the memory data to zero. Select the flash memory areas to be programmed with erase block registers 1 and 2 (EBR1, EBR2). Next set the E bit in FLMCR, selecting erase mode. The erase time is the time during which the E bit is set. To prevent overerasing, use a software timer to divide the time for one erasure, and insure that the total time does not exceed 30 s. See section 6.7.6, Erase Flowcharts and Sample Programs, for the time for one erasure. Overerasing, due to program runaway for example, can give memory cells a negative threshold voltage and cause them to operate incorrectly. Before selecting erase mode, set up the watchdog timer so as to prevent overerasing. 6.7.5 Erase-Verify Mode
In erase-verify mode, after data has been erased, it is read to check that it has been erased correctly. After the erase time has elapsed, exit erase mode (clear the E bit to 0), and select eraseverify mode (set the EV bit to 1). Before reading data in erase-verify mode, write H'FF dummy data to the address to be read. This dummy write applies an erase-verify voltage to the memory cells at the latched address. If the flash memory is read in this state, the data at the latched address will be read. After the dummy write, wait at least 2 s before reading. Also, wait at least 4 s before performing the first dummy write after selecting erase-verify mode. If the read data has been successfully erased, perform the erase-verify sequence (dummy write, wait of at least 2 s, read) on the next address. If the read data has not been erased, select erase mode again and repeat the same erase and erase-verify sequence through the last address, until all memory data has been erased to 1. Do not repeat the erase and erase-verify sequence more than 602 times, however.
Rev. 6.00 Sep 12, 2006 page 132 of 526 REJ09B0326-0600
Section 6 ROM
6.7.6
Erase Flowcharts and Sample Programs
Flowchart for Erasing One Block
Start Set erase block register (set bit for block to be erased to 1) Write 0 data in all addresses to be erased (prewrite)*1 n=1 Enable watchdog timer *2 Select erase mode (E bit = 1 in FLMCR) Wait (x) ms *5 Clear E bit Disable watchdog timer Set block start address as verify address Select erase-verify mode (EV bit = 1) Wait (tvs1) s *6 Dummy write to verify address *3 (flash memory latches address) Wait (tvs2) s *6 Verify *4 (read data H'FF?) OK No Last address? Yes Address + 1 address Clear EV bit Clear erase block register (clear bit for erased block to 0) End of erase Clear EV bit End of erase-verify NG Erasing halts Notes: 1. Program all addresses to be erased by following the prewrite flowchart. 2. Set the watchdog timer overflow interval to the initial value shown in table 6.12. 3. For the erase-verify dummy write, write H'FF using a byte transfer instruction. 4. For the erase-verify operation, read the data using a byte transfer instruction. When erasing multiple blocks, clear the erase block register bits for erased blocks and perform additional erasing only for unerased blocks. 5. Erase time x is successively incremented to initial set value x 2n-1 (n = 1 to 4), and is fixed from the 4th time onward. An initial value of 6.25 ms or less should be set, and the time for one erasure should be 50 ms or less. 6. tvs1: 4 s or more tvs2: 2 s or more N: 602 (set N so that the total erase time does not exceed 30 s)
n N? *6 Yes
No n+1n Yes
Erase error
n > 4? No Double the erase time (x x 2 x)
Figure 6.14 Erase Flowchart
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Section 6 ROM
Prewrite Flowchart
Start Set erase block register (set bit for block to be programmed to 1) Set start address *6 n=1 Write H'00 to flash memory (flash memory latches programmed address and data) *1 Enable watchdog timer *2
Select program mode (P bit = 1 in FLMCR) Wait (x) s *4 Clear P bit Disable watchdog timer Wait (tvs1) s *5
Notes: 1. Write using a byte transfer instruction. 2. For the timer overflow interval, set the timer counter value (TCW) to H'FE. 3. In prewrite-verify mode, P, E, PV, and EV are all cleared to 0, and 12 V is applied to the VPP pin. Read using a byte transfer 4. Programming time x is successively incremented to initial set value x 2n-1 (n = 1 to 6). The initial value should therefore be set to 15.8 s or less to make the total programming time 1 ms or less. 5. tvs1: 4 s or more N: 6 (set N so that the total programming time does not exceed 1 ms) End of programming 6. The start address and last address are the start address and last address of the block to be erased.
Prewrite verify *3 (read data H'00?) OK
NG
Double the programming time (x x 2 x) n+1n n N? *5 Yes No
*6
Programming error No
Address + 1 address
Last address? Yes
Clear erase block register (clear bit for programmed block to 0)
End of prewrite
Figure 6.15 Prewrite Flowchart
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Section 6 ROM
Sample Program for Erasing One Block This program uses the following registers: R0: R2: R3: R4: R5: Used for erase block specification. Also stores address used in prewrite and erase-verify. Stores last address of block to be erased. Stores address used in prewrite and erase-verify. Used for prewrite, prewrite-verify, erase, and erase-verify loop counter value setting. Also stores register set values. Used for prewrite and erase loop counter value setting.
R1H: Stores read data. Also used in dummy write.
R6L: Used for prewrite-verify and erase-verify fail count. The values of #a, #b, #c, #d, and #e in the program depend on the operating frequency. They should be set as indicated in tables 6.11 and 6.12. Erase block register (EBR1, EBR2) settings should be made as indicated in sections 6.5.2 and 6.5.3 in section 6.5, Flash Memory Register Descriptions. For #BLKSTR and #BLKEND, the start address and end address corresponding to the set erase block register should be set as indicated in table 6.7.
FLMCR: EBR1: EBR2: TCSRW: TCW: .EQU .EQU .EQU .EQU .EQU H'FF80 H'FF82 H'FF83 H'FFBE H'FFBF
.ALIGN 2 MOV.B MOV.B #H'**, R0H, R0H @EBR*:8 ; ;Set EBR*
; #BLKSTR is start address of block to be erased ; #BLKEND is last address of block to be erased MOV.W MOV.W ADDS #BLKSTR, R0 #BLKEND, R2 #1, R2 ;Start address of block to be erased ;Last address of block to be erased ;Last address of block to be erased + 1 R2
; Execute prewrite MOV.W R0, R3 ;Start address of block to be erased Rev. 6.00 Sep 12, 2006 page 135 of 526 REJ09B0326-0600
Section 6 ROM PREWRT: MOV.B MOV.W PREWRS: INC MOV.B MOV.B MOV.W MOV.B MOV.B MOV.B MOV.B MOV.W BSET LOOPR1: SUBS MOV.W BNE BCLR MOV.B MOV.B MOV.B LOOPR2: DEC BNE MOV.B BEQ CMP.B BEQ ADD.W BRA #H'00, #H'a, R6L #H'00, R1H, R1H @R3 R6L R5 ;Prewrite verify fail counter ;Set prewrite loop counter ;Prewrite-vector fail counter + 1 R6L ; ;Write H'00 ; ; ; ; ;Start watchdog timer ;Set prewrite loop counter ;Set P bit ; ; ;Wait loop @FLMCR:8 R4L @TCSRW:8 R4H ;Clear P bit ; ;Stop watchdog timer ;Set prewrite-verify loop counter ; ;Wait loop R1H ;Read data = H'00? ;If read data = H'00, branch to PWVFOK R6L ;Prewrite-verify executed 6 times? ;If prewrite-verify executed 6 times, branch to ABEND1 R5 ;Double the programming time ;Prewrite again
#H'FE5A, R4 R4L, R4H, #H'36, R4L, R5, #0, #1, R4, LOOPR1 #0, #H'50, R4L, #H'c, R4H LOOPR2 @R3, PWVFOK #H'06, ABEND1 R5, PREWRS @TCSRW:8 @TCW:8 R4L @TCSRW:8 R4 @FLMCR:8 R4 R4
ABEND1: Write error ;Address + 1 R3 ;Last address? ;If not last address, prewrite next address
PWVFOK: ADDS CMP.W BNE ; Execute erase
#1, R2, PREWRT
R3 R3
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Section 6 ROM ERASES: MOV.W MOV.W ERASE: ADDS MOV.W MOV.B MOV.B MOV.B MOV.B MOV.W BSET LOOPE: NOP NOP NOP NOP SUBS MOV.W BNE BCLR MOV.B MOV.B #1, R4, LOOPE #1, #H'50, R4L, @FLMCR:8 R4L @TCSRW:8 R4 R4 ; ; ;Wait loop ;Clear E bit ; ;Stop watchdog timer #H'0000, R6 #H'd, #1, R5 R6 ;Erase-verify fail counter ;Set erase loop counter ;Erase-verify fail counter + 1 R6 ; ; ; ; ;Start watchdog timer ;Set erase loop counter ;Set E bit
#H'e5A, R4 R4L, R4H, #H'36, R4L, R5, #1, @TCSRW:8 @TCW:8 R4L @TCSRW:8 R4 @FLMCR:8
; Execute erase-verify MOV.W MOV.B BSET LOOPEV: DEC BNE EVR2: MOV.B MOV.B MOV.B LOOPDW: DEC BNE MOV.B CMP.B BNE R0, #H'b, #3, R4H LOOPEV #H'FF, R1H, #H'c, R4H LOOPDW @R3+, #H'FF, RERASE R1H R1H R1H @R3 R4H R3 R4H @FLMCR:8 ;Start address of block to be erased ;Set erase-verify loop counter ;Set EV bit ; ;Wait loop ; ;Dummy write ;Set erase-verify loop counter ; ;Wait loop ;Read ;Read data = H'FF? ;If read data H'FF, branch to RERASE Rev. 6.00 Sep 12, 2006 page 137 of 526 REJ09B0326-0600
Section 6 ROM CMP.W BNE BRA R2, EVR2 OKEND R3 ;Last address in block? ; ; ;Clear EV bit ;Erase-verify address - 1 R3 ; ;Erase-verify fail count = 4? ;If R6 4. branch to BRER (branch until R6 = 4 - 602) R5 ;If R6 < 4, double erase time (executed only for R6 = 1, 2, 3)
RERASE: BCLR SUBS MOV.W CMP.W BPL ADD.W
#3, #1,
@FLMCR:8 R3
#H'0004, R4 R4, BRER R5, R6
BRER:
MOV.W CMP.W BNE BRA
#H'025A, R4 R4, ERASE ABEND2 R6
; ;Erase-verify executed 602 times? ;If erase-verify not executed 602 times, erase again ;If erase-verify executed 602 times, branch to ABEND2 ;Clear EV bit ; ;Clear EBR*
OKEND:
BCLR MOV.B MOV.B
#3, #H'00, R6L,
@FLMCR:8 R6L @EBR*:8
One block erased
ABEND2: Erase error
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Section 6 ROM
Flowchart for Erasing Multiple Blocks
Start Set erase block register (set bit for block to be erased to 1) Write 0 data in all addresses to be erased (prewrite)*1 n=1 Enable watchdog timer *2
Select erase mode (E bit = 1 in FLMCR) Wait (x) ms *5 Clear E bit Disable watchdog timer Select erase-verify mode (EV bit = 1 in FLMCR) Wait (tvs1) s *6
Erase-verify next block Set block start address as verify address Dummy write to verify address *3 (flash memory latches address) Wait (tvs2) s *6 Verify *4 (read data H'FF?) Address + 1 address No OK Last address of block? Yes Clear EBR bit for erase block NG
Erasing halts
Notes: 1. Program all addresses to be erased by following the prewrite flowchart. 2. Set the timer overflow interval to the initial value shown in table 6.13. 3. For the erase-verify dummy write, write H'FF using a byte transfer instruction. 4. For the erase-verify operation, read the data using a byte transfer instruction. When erasing multiple blocks, clear the erase block register bits for erased blocks and perform additional erasing only for unerased blocks. 5. Erase time x is successively incremented to initial set value x 2n-1 (n = 1 to 4), and is fixed from the 4th time onward. An initial value of 6.25 ms or less should be set, and the time for one erasure should be 50 ms or less. 6. tvs1: 4 s or more tvs2: 2 s or more N: 602 (set N so that the total erase time does not exceed 30 s)
Erase-verify next block
Erase-verify completed for all erase blocks? Yes
No
n+1n No Erase-verify completed for all erase blocks? Yes Clear EV bit All erase blocks erased? (EBR1 = EBR2 = 0?) Yes End of erase No Double the erase time (x x 2 x) No n N? *6 Yes Erase error No
n 4?
Yes
Figure 6.16 Multiple-Block Erase Flowchart
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Section 6 ROM
Sample Program for Erasing Multiple Blocks This program uses the following registers: R0: Used for erase block specification (set as explained below). Also stores address used in prewrite and erase-verify.
R1H: Used to test bits 8 to 11 of R0. Stores read data; used in dummy write. R1L: Used to test bits 0 to 11 of R0. R2: R3: R4: R5: Specifies address where address used in prewrite and erase-verify is stored. Stores address used in prewrite and erase-verify. Stores last address of block to be erased. Used for prewrite and erase loop counter value setting.
R6L: Used for prewrite-verify and erase-verify fail count. Arbitrary blocks can be erased by setting bits in R0. R0 settings should be made by writing with a word transfer instruction. A bit map of R0 and a sample setting for erasing specific blocks are shown below.
Bit: R0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LB3 LB2 LB1 LB0 SB7 SB6 SB5 SB4 SB3 SB2 SB1 SB0 Corresponds to EBR2
Corresponds to EBR1 Note: Bits 15 to 12 should be cleared to 0.
Example: To erase blocks LB2, SB7, and SB0
Bit: R0 15 0 14 0 13 0 12 11 10 9 8 7 6 5 4 3 2 1 0
LB3 LB2 LB1 LB0 SB7 SB6 SB5 SB4 SB3 SB2 SB1 SB0 Corresponds to EBR2 0 0 1 0 0 0 0 0 0 1 0 0 1
Corresponds to EBR1
R0 is set as follows:
MOV.W MOV.B MOV.B #H'0481, R0 R0H, R0L, @EBR1 @EBR2
The values of #a, #b, #c, #d, and #e in the program depend on the operating frequency. They should be set as indicated in tables 6.11 and 6.12.
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Section 6 ROM
Notes: 1. In this sample program, the stack pointer (SP) is set to address H'FF80. On-chip RAM addresses H'FF7E and H'FF7F are used as a stack area. Therefore addresses H'FF7E and H'FF7F should not be used when this program is executed, and on-chip RAM should not be disabled. 2. It is assumed that this program, written in the ROM area, is transferred to the RAM area and executed there. For #RAMSTR in the program, substitute the start address of the RAM area to which the program is transferred. The value set for #RAMSTR must be an even number.
FLMCR: EBR1: EBR2: TCSRW: TCW: STACK: .EQU .EQU .EQU .EQU .EQU .EQU H'FF80 H'FF82 H'FF83 H'FFBE H'FFBF H'FF80
START:
.ALIGN 2 MOV.W #STACK,
SP
; Set stack pointer
; Set R0 value as explained on previous page. This sample program erases ; all blocks. MOV.W #H'0FFF, R0 ; Select blocks to be erased (R0: EBR1/EBR2) MOV.B R0H, @EBR1 ; Set EBR1 MOV.B R0L, @EBR2 ; Set EBR2 ; #RAMSTR is start address of RAM area to which program is transferred ; Set #RAMSTR to even number MOV.W #RAMSTR, R2 ; Transfer destination start address (RAM) MOV.W #ERVADR, R3 ; ADD.W R3, R2 ; #RAMSTR + #ERVADR R2 MOV.W #START, R3 ; SUB.W R3, R2 ; Address of data area used in RAM MOV.B PRETST: CMP.B BEQ CMP.B BMI MOV.B SUBX BTST BNE BRA EBR2PW: BTST BNE PWADD1: INC #H'00, #H'0C, ERASES #H'08, EBR2PW R1L, #H'08, R1H, PREWRT R1L, PREWRT R1L R1L R1L R1L R1H R1H R0H PWADD1 R0L ; ; ; ; ; ; ; ; ; ; ; ; ;
Used to test bit R1L in R0 R1L = H'0C? If finished checking all R0 bits, branch to ERASES If R1L 8, EBR1 test; if R1L < 8, EBR2 test R1L - 8 R1H Test bit R1H in EBR1 (R0H) If bit R1H in EBR1 (R0H) is 1, branch to PREWRT If bit R1H in EBR1 (R0H) is 0, branch to PWADD1 Test bit R1L in EBR2 (R0L) If bit R1L in EBR2 (R0L) is 1, branch to PREWRT R1L + 1 R1L
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Section 6 ROM MOV.W @R2+, BRA PRETST ; Execute prewrite PREWRT: MOV.W @R2+, PREW: MOV.B #H'00, MOV.W #H'a, PREWRS: INC R6L MOV.B #H'00 MOV.B R1H, MOV.W #H'FE5A, MOV.B R4L, MOV.B R4H, MOV.B #H'36, MOV.B R4L, MOV.W R5, BSET #0, LOOPR1: SUBS MOV.W BNE BCLR MOV.B MOV.B MOV.B LOOPR2: DEC BNE MOV.B BEQ CMP.B BEQ ADD.W BRA #1, R4, LOOPR1 #0, #H'50, R4L, #H'b, R4H LOOPR2 @R3, PWVFOK #H'06, ABEND1 R5, PREWRS R3 ; Dummy-increment R2 ;
R3 R6L R5
; ; ; ; R1H ; @R3 ; R4 ; @TCSRW:8 ; @TCW:8 ; R4L ; @TCSRW:8 ; R4 ; @FLMCR:8 ; R4 R4
Prewrite start address Prewrite-verify fail counter Set prewrite loop counter Prewrite-verify fail counter + 1 R6H Write H'00
Start watchdog timer Set prewrite loop counter Set P bit
; ; ; @FLMCR:8 ; R4L ; @TCSRW:8 ; R4H ; ; ; ; ; ; ; ; ;
Wait loop Clear P bit Stop watchdog timer Set prewrite-verify loop counter
R1H R6L R5
Wait loop Read data = H'00? If read data = H'00, branch to PWVFOK Prewrite-verify executed 6 times? If prewrite-verify executed 6 times, branch to ABEND1 Double the programming time Prewrite again
ABEND1: Write error PWVFOK: ADDS #1, MOV.W @R2, CMP.W R4, BNE PREW PWADD2: INC R1L BRA PRETST ; Execute erase ERASES: MOV.W #H'0000, MOV.W #H'd, ERASE: ADDS #1, R3 R4 R3 ; ; ; ; ; ;
Address + 1 R3 Start address of next block Last address? If not last address, prewrite next address Used to test bit R1L +1 in R0 Branch to PRETST
R6 R5 R6
; Erase-verify fail counter ; Set erase loop counter ; Erase-verify fail counter + 1 R6
Rev. 6.00 Sep 12, 2006 page 142 of 526 REJ09B0326-0600
Section 6 ROM MOV.W MOV.B MOV.B MOV.B MOV.B MOV.W BSET NOP NOP NOP NOP SUBS MOV.W BNE BCLR MOV.B MOV.B #H'e5A, R4L, R4H, #H'36, R4L, R5, #1, R4 ; @TCSRW:8 ; @TCW:8 ; R4L ; @TCSRW:8 ; Start watchdog timer R4 ; Set erase loop counter @FLMCR:8 ; Set E bit
LOOPE:
#1, R4, LOOPE #1, #H'50, R4L,
R4 R4
; ; ; Wait loop @FLMCR:8 ; Clear E bit R4L ; @TCSRW:8 ; Stop watchdog timer
; Execute erase-verify EVR: MOV.W #RAMSTR, R2 MOV.W #ERVADR, R3 ADD.W R3, R2 MOV.W #START, R3 SUB.W R3, R2 MOV.B MOV.B BSET LOOPEV: DEC BNE EBRTST: CMP.B BEQ CMP.B BMI MOV.B SUBX BTST BNE BRA EBR2EV: BTST BNE ADD01: INC MOV.W BRA ERASE1: BRA ERSEVF: MOV.W #H'00, #H'b, #3, R4H LOOPEV #H'0C, HANTEI #H'08, EBR2EV R1L, #H'08, R1H, ERSEVF ADD01 R1L, ERSEVF R1L @R2+, EBRTST ERASE @R2+, R3
; Transfer destination start address (RAM) ; ; #RAMSTR + #ERVADR R2 ; ; Address of data area used in RAM
Used to test bit R1L in R0 Set erase-verify loop counter Set EV bit Wait loop R1L = H'0C? If finished checking all R0 bits, branch to HANTEI If R1L 8, EBR1 test; if R1L < 8, EBR2 test R1L - 8 R1H Test bit R1H in EBR1 (R0H) If bit R1H in EBR1 (R0H) is 1, branch to ERSEVF If bit R1H in EBR1 (R0H) is 0, branch to ADD01 Test bit R1L in EBR2 (R0L) If bit R1L in EBR2 (R0L) is 1, branch to ERSEVF R1L + 1 R1L Dummy-increment R2
R1L ; R4H ; @FLMCR:8 ; ; ; R1L ; ; R1L ; ; R1H ; R1H ; R0H ; ; ; R0L ; ; ; R3 ; ;
; Branch to ERASE via ERASE1 ; Start address of block to be erase-verified Rev. 6.00 Sep 12, 2006 page 143 of 526 REJ09B0326-0600
Section 6 ROM MOV.B MOV.B MOV.B LOOPEP: DEC BNE MOV.B CMP.B BNE MOV.W CMP.W BNE EVR2: #H'FF, R1H, #H'c, R4H LOOPEP @R3+, #H'FF, BLKAD @R2, R4, EVR2 R1H @R3 R4H ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;
Dummy write Set erase-verify loop counter Wait loop Read Read data = H'FF? If read data H'FF, branch to BLKAD Start address of next block Last address in block?
R1H R1H R4 R3
SBCLR: BLKAD:
CMP.B #H'08, BMI SBCLR MOV.B R1L, SUBX #H'08, BCLR R1H, BRA BLKAD BCLR R1L, INC R1L BRA EBRTST
R1L R1H R1H R0H R0L
If R1L 8, EBR1 test; if R1L < 8, EBR2 test R1L - 8 R1H Clear bit R1H in EBR1 (R0H) Clear bit R1L in EBR2 (R0L) R1L + 1 R1L
HANTEI: BCLR #3, MOV.B R0H, MOV.B R0L, MOV.W R0, BEQ EOWARI MOV.W #H'0004, CMP.W R4, BPL BRER ADD.W R5, BRER: MOV.W #H'025A, CMP.W R4, BNE ERASE1 BRA ABEND2
@FLMCR:8 ; @EBR1:8 ; @EBR2:8 ; R4 ; ; R4 ; R6 ; ; R5 ; R4 R6
Clear EV bit
If EBR1/EBR2 = all 0s, normal end of erase Erase-verify fail count = 4? If R6 4. branch to BRER (branch until R6 = 4 - 602)
If R6 < 4, double erase time (executed only for R6 = 1, 2, 3)
; ; Erase-verify executed 602 times? ; If erase-verify not executed 602 times, erase again ; If erase-verify executed 602 times, branch to ABEND2
;**** < Block address table used in erase-verify > **** .ALIGN 2 ERVADR: .DATA.W H'0000 ; SB0 .DATA.W H'0080 ; SB1 .DATA.W H'0100 ; SB2 .DATA.W H'0180 ; SB3 .DATA.W H'0200 ; SB4 .DATA.W H'0400 ; SB5 .DATA.W H'0800 ; SB6 .DATA.W H'0C00 ; SB7 .DATA.W H'1000 ; LB0 Rev. 6.00 Sep 12, 2006 page 144 of 526 REJ09B0326-0600
Section 6 ROM .DATA.W .DATA.W .DATA.W .DATA.W EOWARI: ABEND2: H'2000 H'4000 H'6000 H'8000 ; ; ; ; LB1 LB2 LB3 FLASH END
; End of erase ; Erase error
Loop Counter and Watchdog Timer Overflow Interval Settings in Programs: The settings of #a, #b, #c, #d, and #e in the program examples depend on the clock frequency. Sample loop counter settings for typical operating frequencies are shown in table 6.11. The value of #e should be set as indicated in table 6.12. As software loops are used, there is intrinsic error, and the calculated value and actual time may not be the same. Therefore, initial values should be set so that the total write time does not exceed 1 ms, and the total erase time does not exceed 30 s. The maximum number of writes in the program examples is set as N = 6. Write and erase operations as shown in the flowcharts are achieved by setting the values of #a, #b, #c, and #d in the program examples as indicated in table 6.11. Use the settings shown in table 6.12 for the value of #e. In these sample programs, wait state insertion is disabled. If wait states are used, the setting should be made after the end of the program. The set value for the watchdog timer (WDT) overflow time is calculated on the basis of the number of instructions including the write time and erase time from the time the watchdog timer is started until it stops. Therefore, no other instructions should be added between starting and stopping of the watchdog timer in these programs.
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Section 6 ROM
Table 6.11 Set Values of #a, #b, #c, and #d for Typical Operating Frequencies when Sample Program Is Executed in On-Chip Memory (RAM)
Oscillation Frequency fOSC = 16 MHz fOSC = 10 MHz fOSC = 8 MHz fOSC = 2 MHz Operating Frequency = 8 MHz Meaning of Variable a () b () c () d () Counter Set Set Time Value
H'000F H'06 H'03 H'0C34
= 5 MHz
= 4 MHz
= 1 MHz
Counter Set Counter Set Counter Set Value Value Value
H'0009 H'04 H'02 H'07A1 H'0007 H'03 H'01 H'061A H'0001 H'01 H'01 H'0186
Programming time 15.8 s (initial set value) tvs1 tvs2 4 s 2 s
Erase time (initial 6.25 ms set value)
Formula: If an operating frequency other than those shown in table 6.11 is used, the values can be calculated using the formula shown below. The calculation is based on an operating frequency () of 5 MHz. For a () and d (), after decimal calculation, round down the first decimal place and convert to hexadecimal so that a () and d () are 15.8 s or less and 6.25 ms or less, respectively. For b () and c (), after decimal calculation, round up the first decimal place and convert to hexadecimal so that b () and c () are 4 s or more and 2 s or more, respectively.
a () to d () = Operating frequency [MHz] 5 x a ( = 5) to d ( = 5)
Rev. 6.00 Sep 12, 2006 page 146 of 526 REJ09B0326-0600
Section 6 ROM
Examples: Sample calculations when executing a program in on-chip memory (RAM) at an operating frequency of 6 MHz
a () = b () = c () = d () = 6 5 6 5 6 5 6 5 x x x 9 = 10.8 10 = H'000A 4 2 = = 4.8 2.4 5 3 = H'05 = H'03
x 1953 = 2343.6 2343 = H'0927
Table 6.12 Watchdog Timer Overflow Interval Settings (Set Value of #e for Operating Frequencies)
Oscillation Frequency fOSC = 16 MHz Variable e () = 8 MHz
H'9B
fOSC = 10 MHz = 5 MHz
H'DF
fOSC = 8 MHz = 4 MHz
H'E5
fOSC = 2 MHz = 1 MHz
H'F7
Operating Frequency
6.7.7
Prewrite-Verify Mode
Prewrite-verify mode is a verify mode used to all bits to equalize their threshold voltages before erasure. To program all bits, write H'00 in accordance with the prewrite algorithm shown in figure 6.15. Use this procedure to set all data in the flash memory to H'00 after programming. After the necessary programming time has elapsed, exit program mode (by clearing the P bit to 0) and select prewrite-verify mode (leave the P, E, PV, and EV bits all cleared to 0). In prewrite-verify mode, a prewrite-verify voltage is applied to the memory cells at the read address. If the flash memory is read in this state, the data at the read address will be read. After selecting prewrite-verify mode, wait at least 4 s before reading. Note: For a sample prewriting program, see the prewrite subroutine in the sample erasing program.
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Section 6 ROM
6.7.8
Protect Modes
There are two modes for flash memory program/erase protection: hardware protection and software protection. These two protection modes are described below. Software Protection: With software protection, setting the P or E bit in the flash memory control register (FLMCR) does not cause a transition to program mode or erase mode. Details of software protection are given below.
Functions Item Block protect Description Programming and erase protection can be set for individual blocks by settings in the erase block registers (EBR1 and EBR2). Setting EBR1 to H'F0 and EBR2 to H'00 places all blocks in the program/eraseprotected state. Note: * Three modes: program-verify, erase-verify, and prewrite-verify. Program Disabled Erase Disabled Verify* Enabled
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Hardware Protection: Hardware protection refers to a state in which programming/erasing of flash memory is forcibly suspended or disabled. At this time, the flash memory control register (FLMCR) and erase block register (EBR1 and EBR2) settings are cleared. Details of the hardware protection states are given below.
Functions Item Programming voltage (FVPP) protect Description Program Erase Disabled*
2 1 Verify*
When 12 V is not being applied to the Disabled FVPP pin, FLMCR, EBR1, and EBR2 are initialized, and the program/eraseprotected state is entered. To obtain this protection, the VPP voltage should not exceed the VCC power supply 3 voltage.* In a reset, (including a watchdog timer Disabled reset), and in sleep, subsleep, watch, and standby mode, FLMCR, EBR1, and EBR2 are initialized, and the program/erase-protected state is entered. In a reset via the RES pin, the reset state is not reliably entered unless the RES pin is held low for at 4 least 20 ms (oscillation settling time)* after powering on. In the case of a reset during operation, the RES pin must be held low for a minimum of 10 system clock cycles (10).
Disabled
Reset/standby protect
Disabled*
2
Disabled
Notes: 1. 2. 3. 4.
Three modes: program-verify, erase-verify, and prewrite-verify. All blocks are erase-disabled, and individual block specification is not possible. For details, see section 6.9, Flash Memory Programming and Erasing Precautions. For details, see AC Characteristics in section 13, Electrical Characteristics.
6.7.9
Interrupt Handling during Flash Memory Programming/Erasing
If an interrupt is generated while the flash memory is being programmed or erased (while the P or E bit is set in FLMCR), an operating state may be entered in which the vector will not be read correctly in the exception handling sequence, resulting in program runaway. All interrupt sources should therefore be masked to prevent interrupt generation while programming or erasing the flash memory.
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Section 6 ROM
6.8
6.8.1
Flash Memory PROM Mode (H8/3644F, H8/3643F, and H8/3642AF)
PROM Mode Setting
The H8/3644F, H8/3643F, and H8/3642AF, in which the on-chip ROM is flash memory, have a PROM mode as well as the on-board programming modes for programming and erasing flash memory. In PROM mode, the on-chip ROM can be freely programmed using a general-purpose PROM programmer. 6.8.2 Memory Map
Figure 6.17 shows the memory map in PROM mode.
MPU mode H'0000 On-chip ROM area H8/3644F PROM mode H'0000
H'7FFF*
H'7FFF*
"1" output
H'1FFFF Note: * This example applies to the H8/3644F. This address is H'5FFF in the H8/3643F, and H'3FFF in the H8/3642AF.
Figure 6.17 Memory Map in PROM Mode
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Section 6 ROM
6.8.3
Operation in PROM Mode
The program/erase/verify specifications in PROM mode are the same as for the standard HN28F101 flash memory. The H8/3644F, H8/3643F, and H8/3642AF do not have a device recognition code, so the programmer cannot read the device name automatically. Table 6.13 shows how the different operating modes are selected when using PROM mode. Table 6.13 Operating Mode Selection in PROM Mode
Pins Mode Read Read Output disable Standby Command write Read Output disable Standby Write
FVPP VCC CE OE WE D7 to D0 A16 to A0
VCC* VCC* VCC* VPP VPP VPP VPP
VCC VCC VCC VCC VCC VCC VCC
L L H L L H L
L H X L H X H
H H X H H X L
Data output High impedance High impedance Data output High impedance High impedance Data input
Address input
Legend: L: Low level H: High level VPP: VPP level VCC: VCC level X: Don't care Note: * In these states, the FVPP pin must be set to VCC.
VH: 11.5 V VH 12.5 V
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Table 6.14 PROM Mode Commands
1st Cycle Command Memory read Erase setup/erase Erase-verify Auto-erase setup/ auto-erase Program setup/ program Program-verify Reset Cycles 1 2 2 2 2 2 2 Mode Write Write Write Write Write Write Write Address X X EA X X X X Data H'00 H'20 H'A0 H'30 H'40 H'C0 H'FF Mode Read Write Read Write Write Read Write 2nd Cycle Address RA X X X PA X X Data Dout H'20 EVD H'30 PD PVD H'FF
Legend: PA: Program address EA: Erase-verify address RA: Read address PD: Program data PVD: Program-verify output data EVD: Erase-verify output data
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Section 6 ROM
High-Speed, High-Reliability Programming: Unused areas of the flash memory in the H8/3644F, H8/3643F, or H8/3642AF contain H'FF data (initial value). The flash memory uses a high-speed, high-reliability programming procedure. This procedure provides higher programming speed without subjecting the device to voltage stress and without sacrificing the reliability of the programmed data. Figure 6.18 shows the basic high-speed, high-reliability programming flowchart. Tables 6.15 and 6.16 list the electrical characteristics during programming.
Start Set VPP = 12.0 V 0.6 V Address = 0 n=0 n+1n Program setup command Program command Wait (25 s) Program-verify command Wait (6 s) Address + 1 address Verify? OK No Last address? Yes Set VPP = VCC NG No
n = 20? Yes
End
Error
Figure 6.18 High-Speed, High-Reliability Programming
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Section 6 ROM
High-Speed, High-Reliability Erasing: The flash memory in the H8/3644F, H8/3643F, and H8/3642AF uses a high-speed, high-reliability erasing procedure. This procedure provides higher erasing speed without subjecting the device to voltage stress and without sacrificing the reliability of data reliability. Figure 6.19 shows the basic high-speed, high-reliability erasing flowchart. Tables 6.15 and 6.16 list the electrical characteristics during erasing.
Start Program all bits to 0* Address = 0 n=0 n+1n Erase setup/erase command Wait (10 ms) Erase-verify command Wait (6 s) Address + 1 address Verify? OK No Last address? Yes End Error
NG n = 3000? Yes No
Note: * Follow the high-speed, high-reliability programming flowchart in programming all bits. If 0 has already been written, perform programming for unprogrammed bits.
Figure 6.19 High-Speed, High-Reliability Erasing
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Section 6 ROM
Table 6.15 DC Characteristics in PROM Mode (Conditions: VCC = 5.0 V 10%, VPP = 12.0 V 0.6 V, VSS = 0 V, Ta = 25C 5C)
Item Input high voltage Input low voltage Symbol Min FO7 to FO0, FA16 to FA0, VIH OE, CE, WE FO7 to FO0, FA16 to FA0, VIL OE, CE, WE VOH VOL 2.2 -0.3 2.4 Typ Max Unit Test Conditions
VCC + 0.3 V 0.8 0.45 2 V V V A IOH = -200 A IOL = 1.6 mA Vin = 0 to VCC
Output high FO7 to FO0 voltage Output low voltage Input leakage current VCC current FO7 to FO0
FO7 to FO0, FA16 to FA0, | ILI | OE, CE, WE Read Program Erase Read Program Erase ICC ICC ICC IPP IPP IPP

40 40 40 10 20 20
80 80 80 10 20 40 40
mA mA mA A mA mA mA VPP = 2.7 to 5.5 V VPP = 12.6 V VPP = 12.6 V VPP = 12.6 V
FVPP current
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Section 6 ROM
Table 6.16 AC Characteristics in PROM Mode (Conditions: VCC = 5.0 V 10%, VPP = 12.0 V 0.6 V, VSS = 0 V, Ta = 25C 5C)
Item Command write cycle Address setup time Address hold time Data setup time Data hold time CE setup time CE hold time VPP setup time VPP hold time WE programming pulse width WE programming pulse high time OE setup time before command write OE setup time before verify Verify access time OE setup time before status polling Status polling access time Program wait time Erase wait time Output disable time Total auto-erase time Symbol tCWC tAS tAH tDS tDH tCES tCEH tVPS tVPH tWEP tWEH tOEWS tOERS tVA tOEPS tSPA tPPW tET tDF tAET Min 120 0 60 50 10 0 0 100 100 70 40 0 6 120 25 9 0 0.5 Typ Max 500 120 11 40 30 Unit ns ns ns ns ns ns ns ns ns ns ns ns s ns ns ns s ms ns s Test Conditions Figure 6.20 Figure 6.21* Figure 6.22
Notes: The CE, OE, and WE pins should be driven high during transitions of VPP from 5 V to 12 V and from 12 V to 5 V. * Input pulse level: 0.45 V to 2.4 V Input rise time and fall time 10 ns Timing reference levels: 0.8 V and 2.0 V for input; 0.8 V and 2.0 V for output
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Auto-erase and status polling
Auto-erase setup VCC VPP 5.0 V 12 V 5.0 V Address CE tCEH OE tOEWS WE tDS I/O7
Command input
tVPS
tVPH
tCES tOEPS
tCES tWEP tCEH
tCWC tCES tWEH tDH tDS
Command input
tWEP
tAET tDF tDH tSPA
Status polling I/O0 to I/O6
Command input Command input
Figure 6.20 Auto-Erase Timing
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Section 6 ROM
Program setup VCC VPP 5.0 V 12 V 5.0 V Address tVPS tVPH
Valid address
Program
Program-verify
tAS CE
tAH
tCEH OE tOEWS WE tDS I/O7
Command input
tCES tWEP
tCWC tCEH tCES t WEP tPPW
tCES tWEP
tCEH tOERS tVA
tWEH tDH tDS
Command input
tDH
tDS
Command input
tDH
Valid data output
tDF
I/O0 to I/O6
Command input
Command input
Command input
Valid data output
Note: Program-verify data output values maybe intermediate between 1 and 0 if programming is insufficient.
Figure 6.21 High-Speed, High-Reliability Programming Timing
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Section 6 ROM
Erase setup VCC VPP 5.0 V 12 V 5.0 V tVPS tVPH Address Valid address tAS tAH Erase Erase -verify
CE
OE
tOEWS tCES tWEP
tCWC tCES tCEH tDS tDH
tCEH tWEP
tCES tET
tCEH tWEP tOERS
WE
tWEH tDS tDH tDS tDH
tVA tDF
Valid data output
I/O0 to I/O7
Command input
Command input
Command input
Note: Erase -verify data output values maybe intermediate between 1 and 0 if erasing is insufficient.
Figure 6.22 Erase Timing
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Section 6 ROM
6.9
Flash Memory Programming and Erasing Precautions
Precautions concerning the use of on-board programming modes and PROM mode are summarized below. 1. Program with the specified voltages and timing. The rated programming voltage (VPP) of the flash memory is 12.0 V. If the PROM programmer is set to Renesas HN28F101 specifications, VPP will be 12.0 V. Applied voltages in excess of the rating can permanently damage the device. In particular, insure that the peak overshoot of the PROM programmer does not exceed the maximum rating of 13 V. 2. Before programming, check that the chip is correctly mounted in the PROM programmer. Overcurrent damage to the device can result if the index marks on the PROM programmer socket, socket adapter, and chip are not correctly aligned. 3. Do not touch the socket adapter or chip while programming. Touching either of these can cause contact faults and write errors. 4. Set H'FF as the PROM programmer buffer data for the following addresses: H8/3644F: H'8000 to H'1FFFF H8/3643F: H'6000 to H'1FFFF H8/3642AF: H'4000 to H'1FFFF The size of the PROM area is 32 kbytes in the H8/3644F, 24 kbytes in the H8/3643F, and 16 kbytes in the H8/3642AF. The addresses shown above always read H'FF, so if H'FF is not specified as programmer data, a block error will occur. 5. Precautions in applying, releasing, and cutting*1 the programming voltage (VPP) a. Apply the programming voltage (VPP) after VCC has stabilized, and release VPP before cutting VCC. To avoid programming or erasing flash memory by mistake, VPP should only be applied, released, and cut when the MCU is in a "stable operating condition" as described below. MCU stable operating condition * The VCC voltage must be within the rated voltage range (VCC = 2.7 V to 5.5 V). If the VPP voltage is applied, released, or cut while VCC is not within its rated voltage range (VCC = 2.7 V to 5.5 V), since the MCU is unstable, the flash memory may be programmed or erased by mistake. This can occur even if VCC = 0 V. Adequate power supply measures should be taken, such as the insertion of a bypass capacitor, to prevent fluctuation of the VCC power supply when VPP is applied.
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* Oscillation must have stabilized (following the elapse of the oscillation settling time) or be stopped. When the VCC power is turned on, hold the RES pin low for the duration of the oscillation settling time*2 (trc = 20 ms) before applying VPP. * The MCU must be in the reset state, or in a state in which reset has ended normally (reset has been released) and flash memory is not being accessed. Apply or release VPP either in the reset state, or when the CPU is not accessing flash memory (when a program in on-chip RAM or external memory is executing). Flash memory data cannot be read normally at the instant when VPP is applied or released, so do not read flash memory while VPP is being applied or released. For a reset during operation, apply or release VPP only after the RES pin has been held low for at least 10 system clock cycles (10). * The P and E bits must be cleared in the flash memory control register (FLMCR). When applying or releasing VPP, make sure that the P or E bit is not set by mistake. * There must be no program runaway. When VPP is applied, program execution must be supervised, e.g. by the watchdog timer. These power-on and power-off timing requirements for VCC and VPP should also be satisfied in the event of a power failure and in recovery from a power failure. If these requirements are not satisfied, overprogramming or overerasing may occur due to program runaway, etc., which could cause memory cells to malfunction. b. The VPP flag is set and cleared by a threshold decision on the voltage applied to the FVPP pin. The threshold level is approximately in the range from VCC +2 V to 11.4 V. When this flag is set, it becomes possible to write to the flash memory control register (FLMCR) and the erase block registers (EBR1 and EBR2), even though the VPP voltage may not yet have reached the programming voltage range of 12.0 V 0.6 V. Do not actually program or erase the flash memory until VPP has reached the programming voltage range. The programming voltage range for programming and erasing flash memory is 12.0 V 0.6 V (11.4 V to 12.6 V). Programming and erasing cannot be performed correctly outside this range. When not programming or erasing the flash memory, insure that the VPP voltage does not exceed the VCC voltage. This will prevent unintentional programming and erasing. Notes: 1. Definitions of VPP application, release, and cut-off are as follows: Application: Release: Cut-off: Raising the voltage from VCC to 12.0 V 0.6 V Dropping the voltage from 12.0 V 0.6 V to VCC Halting voltage application (floating state)
2. The time depends on the resonator used; refer to the electrical characteristics.
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Section 6 ROM
tOSC1
3.0 to 5.5 V VCC 0 s min. 12 0.6 V VCC + 2 V to 11.4 V VCCV VPP (boot mode) 0 s min. Timing of boot program branch to RAM space 12 0.6 V 0 to VCCV 0 s min.
VCCV VPP (user program mode)
0 to VCCV
RES
Period during which flash memory access is prohibited and VPP flag set/clear period
Min. 10 cycles (When RES is low)
Figure 6.23 VPP Power-On and Cut-Off Timing 6. Do not apply 12 V to the FVPP pin during normal operation. To prevent erroneous programming or erasing due to program runaway, etc., apply 12 V to the FVPP pin only when programming or erasing flash memory. If overprogramming or overerasing occurs due to program runaway, etc., the memory cells may not operate normally. A system configuration in which a high level is constantly applied to the FVPP pin should be avoided. Also, while a high level is applied to the FVPP pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc.
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7. Design a current margin into the programming voltage (VPP) power supply. Insure that VPP remains within the range 12.0 V 0.6 V (11.4 V to 12.6 V) during programming and erasing. Programming and erasing may become impossible outside this range. 8. Insure that peak overshoot at the FVPP and TEST pins does not exceed the maximum rating. Connect bypass capacitors as close as possible to the FVPP and TEST pins. In boot mode start-up, also, bypass capacitors should be connected to the TEST pin in the same way.
12 V
FVPP H8/3644F 1.0 F 0.01 F
Figure 6.24 Example of VPP Power Supply Circuit Design 9. Use the recommended algorithms when programming and erasing flash memory. The recommended algorithms enable programming and erasing to be carried out without subjecting the device to voltage stress or sacrificing program data reliability. When setting the program (P) or erase (E) bit in the flash memory control register (FLMCR), the watchdog timer should be set beforehand to prevent the specified time from being exceeded. 10. For comments on interrupt handling while flash memory is being programmed or erased, see section 6.7.9, Interrupt Handling during Flash Memory Programming/Erasing. 11. Notes on accessing flash memory control registers a. Flash memory control register access state in each operating mode The H8/3644F, H8/3643F, and H8/3642AF have flash memory control registers located at addresses H'FF80 (FLMCR), H'FF82 (EBR1), and H'FF83 (EBR2). These registers can only be accessed when 12 V is applied to the flash memory programming power supply pin, FVPP. b. To check for 12 V application/non-application in user mode When address H'FF80 is accessed in user mode, if 12 V is being applied to FVPP, FLMCR is read/written to, and its initial value after reset is H'80. When 12 V is not being applied to FVPP, FLMCR is a reserved area that cannot be modified and always reads H'FF. Since bit 7 (corresponding to the VPP bit) is set to 1 at this time regardless of whether or not 12 V is applied to FVPP, application or release of 12 V to FVPP cannot be determined simply from
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Section 6 ROM
the 0 or 1 status of this bit. A byte data comparison is necessary to check whether 12V is being applied. The relevant coding is shown below.
. . MOV.B CMP.B BEQ . . .
LABEL1:
@H'FF80, R1L #H'FF, R1L LABEL1
Sample program for detection of 12 V application to FVPP (user mode) Table 6.17 Flash Memory DC Characteristics VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, AVREF = 3.0 V to AVCC, VSS = AVSS = 0 V, VPP = 12.0 V 0.6 V Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications)
Item High voltage (12 V) application criterion level* FVPP current FVPP, TEST Symbol VH Min Typ Max 11.4 Unit V Test Conditions
VCC + 2
Read Program Erase
IPP

10 20 20
10 20 40 40
A mA mA mA
VPP = 2.7 to 5.5 V VPP = 12.6 V
Note:
*
The high voltage application criterion level is as shown in the table above, but a setting of 12.0 V 0.6 V should be made in boot mode and when programming and erasing flash memory.
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Section 6 ROM
Table 6.18 Flash Memory AC Characteristics VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, AVREF = 3.0 V to AVCC, VSS = AVSS = 0 V, VPP = 12.0 V 0.6 V Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications)
Item
12 Programming time* * 13 Erase time* *
Symbol tP tE NWEC tVS1 tVS2 *4 tFRS
Min 4 2 50 100
Typ 50 1
Max 1000 30 100
Unit s s Times s s s
Test Conditions
Reprogramming capability 1 Verify setup time 1* Verify setup time 2*
1
Flash memory read setup time
VCC 4.5 V VCC < 4.5 V
Notes: 1. Follow the program/erase algorithms shown in section 6 when making the settings. 2. Indicates the programming time per byte (the time during which the P bit is set in the flash memory control register (FLMCR)). Does not include the program-verify time. 3. Indicates the time to erase all blocks (32 kB) (the time during which the E bit is set in FLMCR). Does not include the prewrite time before erasing of the erase-verify time. 4. After powering on when using an external clock, when the programming voltage (VPP) is switched from 12 V to VCC, an interval at least equal to the read setup time must be allowed to elapse before reading the flash memory. When VPP is released, this specifies the setup time from the point at which the VPP voltage reaches the VCC + 2 V level until the flash memory is read.
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Section 7 RAM
Section 7 RAM
7.1 Overview
The H8/3644 Group has 1 kbyte and 512 byte of high-speed static RAM on-chip. The RAM is connected to the CPU by a 16-bit data bus, allowing high-speed 2-state access for both byte data and word data. 7.1.1 Block Diagram
Figure 7.1 shows a block diagram of the on-chip RAM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'FB80 H'FB82
H'FB80 H'FB82
H'FB81 H'FB83
On-chip RAM H'FF7E H'FF7E Even-numbered address H'FF7F Odd-numbered address
Figure 7.1 RAM Block Diagram
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Section 7 RAM
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Section 8 I/O Ports
Section 8 I/O Ports
8.1 Overview
The H8/3644 Group is provided with three 8-bit I/O ports, three 5-bit I/O ports, two 3-bit I/O ports, and one 8-bit input-only port. Table 8.1 indicates the functions of each port. Each port has of a port control register (PCR) that controls input and output, and a port data register (PDR) for storing output data. Input or output can be assigned to individual bits. See section 2.9.2, Notes on Bit Manipulation, for information on executing bit-manipulation instructions to write data in PCR or PDR. Block diagrams of each port are given in appendix C, I/O Port Block Diagrams. Table 8.1
Port Port 1
Port Functions
Pins P17/IRQ3/TRGV P16 to P15/ IRQ2 to IRQ1 P14/PWM P10/TMOW Other Functions External interrupt 3, timer V trigger input External interrupts 2 and 1 14-bit PWM output Timer A clock output SCI3 data output SCI3 data input SCI3 clock input/output SCI1 data output (SO1), data input (SI1), clock input/output (SCK1) INT interrupt 7 INT interrupt 6 Timer B1 event input INT interrupt 5 A/D converter external trigger input INT interrupts 4 to 0 PMR1 PMR1 PMR7 SCR3 SCR3, SMR PMR3 Function Switching Register PMR1
Description * * 5-bit I/O port Input pull-up MOS selectable
Port 2
*
3-bit I/O port
P22/TxD P21/RxD P20/SCK1
Port 3
* *
3-bit I/O port Input pull-up MOS selectable 8-bit I/O port Input pull-up MOS
P32/SO1 P31/SI1 P30/SCK1 P57 /INT7 P56 /INT6/ TMIB P55/INT5/ ADTRG P54 to P50/ INT4 to INT0
Port 5
* *
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Section 8 I/O Ports Function Switching Register
Port Port 6
Description * * 8-bit I/O port High-current port 5-bit I/O port
Pins P67 to P60
Other Functions
Port 7
*
P77 P76/TMOV P75/TMCIV P74/TMRIV P73 Timer V compare-match output Timer V clock input Timer V reset input TCSRV
Port 8
*
8-bit I/O port
P87 P86/FTID P85/FTIC P84/FTIB P83/FTIA P82/FTOB P81/FTOA P80/FTCI P90* to P94 PB7 to PB0/ AN7 to AN0 Timer X input capture D input Timer X input capture C input Timer X input capture B input Timer X input capture A input Timer X output compare B TOCR output Timer X output compare A TOCR output Timer X clock input A/D converter analog input (AN7 to AN0)
Port 9 Port B Note:
* * *
5-bit I/O port 8-bit input port
There is no P90 function in the flash memory version since P90 is used as the FVPP pin.
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Section 8 I/O Ports
8.2
8.2.1
Port 1
Overview
Port 1 is a 5-bit I/O port. Figure 8.1 shows its pin configuration.
P1 7 /IRQ 3 /TRGV P1 6 /IRQ 2 Port 1 P1 5 /IRQ 1 P1 4 /PWM P1 0 /TMOW
Figure 8.1 Port 1 Pin Configuration 8.2.2 Register Configuration and Description
Table 8.2 shows the port 1 register configuration. Table 8.2
Name Port data register 1 Port control register 1 Port pull-up control register 1 Port mode register 1
Port 1 Registers
Abbr. PDR1 PCR1 PUCR1 PMR1 R/W R/W W R/W R/W Initial Value H'00 H'00 H'00 H'04 Address H'FFD4 H'FFE4 H'FFED H'FFFC
Port Data Register 1 (PDR1)
Bit Initial value Read/Write Note: * 7 P17 0 R/W 6 P16 0 R/W 5 P15 0 R/W 4 P14 0 R/W 3 0* 2 0* 1 0* 0 P10 0 R/W
Bits 3 to 1 are reserved; they are always read as 0 and cannot be modified.
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Section 8 I/O Ports
PDR1 is an 8-bit register that stores data for port 1 pins P17 through P14 and P10. If port 1 is read while PCR1 bits are set to 1, the values stored in PDR1 are read, regardless of the actual pin states. If port 1 is read while PCR1 bits are cleared to 0, the pin states are read. Upon reset, PDR1 is initialized to H'00. Port Control Register 1 (PCR1)
Bit Initial value Read/Write 7 PCR17 0 W 6 PCR16 0 W 5 PCR15 0 W 4 PCR14 0 W 3 0 2 0 1 0 0 PCR10 0 W
PCR1 is an 8-bit register for controlling whether each of the port 1 pins P17 through P14 and P10 functions as an input pin or output pin. Setting a PCR1 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR1 and in PDR1 are valid only when the corresponding pin is designated in PMR1 as a general I/O pin. Upon reset, PCR1 is initialized to H'00. PCR1 is a write-only register, which is always read as all 1s. Port Pull-Up Control Register 1 (PUCR1)
Bit Initial value Read/Write Note: * 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0* 2 0* 1 0* 0 PUCR10 0 R/W
PUCR17 PUCR16 PUCR15 PUCR14
Bits 3 to 1 are reserved; they are always read as 0 and cannot be modified.
PUCR1 controls whether the MOS pull-up of each of the port 1 pins P17 through P14 and P10 is on or off. When a PCR1 bit is cleared to 0, setting the corresponding PUCR1 bit to 1 turns on the MOS pull-up for the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up. Upon reset, PUCR1 is initialized to H'00.
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Section 8 I/O Ports
Port Mode Register 1 (PMR1)
Bit Initial value Read/Write 7 IRQ3 0 R/W 6 IRQ2 0 R/W 5 IRQ1 0 R/W 4 PWM 0 R/W 3 0 2 1 1 0 0 TMOW 0 R/W
PMR1 is an 8-bit read/write register, controlling the selection of pin functions for port 1 pins. Upon reset, PMR1 is initialized to H'04. Bit 7 P17/IRQ3/TRGV Pin Function Switch (IRQ3): This bit selects whether pin IRQ P17/IRQ3/TRGV is used as P17 or as IRQ3/TRGV.
Bit 7: IRQ3 0 1 Description Functions as P17 I/O pin Functions as IRQ3/TRGV input pin (initial value)
Note: Rising or falling edge sensing can be designated for IRQ3. Rising, falling, or both edge sensing can be designated for TRGV. For details on TRGV settings, see section 9.4.2, Register Descriptions.
Bit 6 P16/IRQ2 Pin Function Switch (IRQ2): This bit selects whether pin P16/IRQ2 is used as IRQ P16 or as IRQ2.
Bit 6: IRQ2 0 1 Description Functions as P16 I/O pin Functions as IRQ2 input pin (initial value)
Note: Rising or falling edge sensing can be designated for IRQ2.
Bit 5 P15/IRQ1 Pin Function Switch (IRQ1): This bit selects whether pin P15/IRQ1 is used as IRQ P15 or as IRQ1.
Bit 5: IRQ1 0 1 Description Functions as P15 I/O pin Functions as IRQ1 input pin (initial value)
Note: Rising or falling edge sensing can be designated for IRQ1.
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Section 8 I/O Ports
Bit 4 P14/PWM Pin Function Switch (PWM): This bit selects whether pin P14/PWM is used as P14 or as PWM.
Bit 4: PWM 0 1 Description Functions as P14 I/O pin Functions as PWM output pin (initial value)
Bit 3Reserved Bit: Bit 3 is reserved: it is always read as 0 and cannot be modified. Bit 2 Reserved Bit: Bit 2 is reserved: it is always read as 1 and cannot be modified. Bit 1 Reserved Bit: Bit 1 is reserved: it is always read as 0 and cannot be modified. Bit 0 P10/TMOW Pin Function Switch (TMOW): This bit selects whether pin P10/TMOW is used as P10 or as TMOW.
Bit 0: TMOW 0 1 Description Functions as P10 I/O pin Functions as TMOW output pin (initial value)
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Section 8 I/O Ports
8.2.3
Pin Functions
Table 8.3 shows the port 1 pin functions. Table 8.3
Pin
Port 1 Pin Functions
Pin Functions and Selection Method IRQ3 PCR17 Pin function 0 0 1 P17 input pin P17 output pin 1 * IRQ3/TRGV input pin
P17/IRQ3/TRGV The pin function depends on bit IRQ3 in PMR1 and bit PCR17 in PCR1.
P16/IRQ2 P15/IRQ1
The pin function depends on bits IRQ2 and IRQ1 in PMR1 and bit PCR1n in PCR1. (m = n - 4, n = 6, 5) IRQm PCR1n Pin function 0 0 1 P1n input pin P1n output pin 1 * IRQm input pin
P14/PWM
The pin function depends on bit PWM in PMR1 and bit PCR14 in PCR1. PWM PCR14 Pin function 0 0 1 P14 input pin P14 output pin 1 * PWM output pin
P10/TMOW
The pin function depends on bit TMOW in PMR1 and bit PCR10 in PCR1. TMOW PCR10 Pin function 0 0 1 P10 input pin P10 output pin 1 * TMOW output pin
Legend: * Don't care
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Section 8 I/O Ports
8.2.4
Pin States
Table 8.4 shows the port 1 pin states in each operating mode. Table 8.4
Pins P16/IRQ2
Port 1 Pin States
Reset Sleep Subsleep Standby Watch Subactive Active
Retains Retains P17/IRQ3/TRGV Highimpedance previous previous state state P15/IRQ1 P14/PWM P10/TMOW Note: *
Retains Functional Functional Highimpedance* previous state
A high-level signal is output when the MOS pull-up is in the on state.
8.2.5
MOS Input Pull-Up
Port 1 has a built-in MOS input pull-up function that can be controlled by software. When a PCR1 bit is cleared to 0, setting the corresponding PUCR1 bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a reset.
PCR1n PUCR1n MOS input pull-up Legend: * Don't care Note: n = 7 to 4, 0 0 Off 0 1 On 1 * Off
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Section 8 I/O Ports
8.3
8.3.1
Port 2
Overview
Port 2 is a 3-bit I/O port, configured as shown in figure 8.2.
P2 2 /TXD Port 2 P2 1 /RXD P2 0 /SCK3
Figure 8.2 Port 2 Pin Configuration 8.3.2 Register Configuration and Description
Table 8.5 shows the port 2 register configuration. Table 8.5
Name Port data register 2 Port control register 2
Port 2 Registers
Abbr. PDR2 PCR2 R/W R/W W Initial Value H'00 H'00 Address H'FFD5 H'FFE5
Port Data Register 2 (PDR2)
Bit Initial value Read/Write Note: * 7 0* 6 0* 5 0* 4 0* 3 0* 2 P22 0 R/W 1 P21 0 R/W 0 P20 0 R/W
Bits 7 to 3 are reserved; they are always read as 0 and cannot be modified.
PDR2 is an 8-bit register that stores data for port 2 pins P22 to P20. If port 2 is read while PCR2 bits are set to 1, the values stored in PDR2 are read, regardless of the actual pin states. If port 2 is read while PCR2 bits are cleared to 0, the pin states are read. Upon reset, PDR2 is initialized to H'00.
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Section 8 I/O Ports
Port Control Register 2 (PCR2)
Bit Initial value Read/Write 7 0 6 0 5 0 4 0 3 0 2 PCR22 0 W 1 PCR21 0 W 0 PCR20 0 W
PCR2 is an 8-bit register for controlling whether each of the port 1 pins P22 to P20 functions as an input pin or output pin. Setting a PCR2 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR2 and PDR2 are valid only when the corresponding pin is designated in SCR3 as a general I/O pin. Upon reset, PCR2 is initialized to H'00. PCR2 is a write-only register, which is always read as all 1s.
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Section 8 I/O Ports
8.3.3
Pin Functions
Table 8.6 shows the port 2 pin functions. Table 8.6
Pin P22/TXD
Port 2 Pin Functions
Pin Functions and Selection Method The pin function depends on bit TXD in PMR7 and bit PCR22 in PCR2. TXD PCR22 Pin function 0 0 1 P22 input pin P22 output pin 1 * TXD output pin
P21/RXD
The pin function depends on bit RE in SCR3 and bit PCR21 in PCR2. RE PCR21 Pin function 0 0 1 P21 input pin P21 output pin 1 * RXD input pin
P20/SCK3
The pin function depends on bits CKE1 and CKE0 in SCR3, bit COM in SMR, and bit PCR20 in PCR2. CKE1 CKE0 COM PCR20 Pin function 0 0 1 P20 input pin P20 output pin 0 1 * 0 1 * 1 * * *
SCK3 output SCK3 input pin pin
Legend: * Don't care
8.3.4
Pin States
Table 8.7 shows the port 2 pin states in each operating mode. Table 8.7
Pins P22/TXD P21/RXD P20/SCK3
Port 2 Pin States
Reset Highimpedance Sleep Retains previous state Subsleep Retains previous state Standby Highimpedance Watch Subactive Active Retains Functional Functional previous state
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Section 8 I/O Ports
8.4
8.4.1
Port 3
Overview
Port 3 is a 8-bit I/O port, configured as shown in figure 8.3.
P3 2 /SO 1 Port 3 P3 1 /SI1 P3 0 /SCK1
Figure 8.3 Port 3 Pin Configuration 8.4.2 Register Configuration and Description
Table 8.8 shows the port 3 register configuration. Table 8.8
Name Port data register 3 Port control register 3 Port pull-up control register 3 Port mode register 3 Port mode register 7
Port 3 Registers
Abbr. PDR3 PCR3 PUCR3 PMR3 PMR7 R/W R/W W R/W R/W R/W Initial Value H'00 H'00 H'00 H'00 H'F8 Address H'FFD6 H'FFE6 H'FFEE H'FFFD H'FFFF
Port Data Register 3 (PDR3)
Bit Initial value Read/Write Note: * 7 0* 6 0* 5 0* 4 0* 3 0* 2 P32 0 R/W 1 P31 0 R/W 0 P30 0 R/W
Bits 7 to 3 are reserved; they are always read as 0 and cannot be modified.
PDR3 is an 8-bit register that stores data for port 3 pins P32 to P30. If port 3 is read while PCR3 bits are set to 1, the values stored in PDR3 are read, regardless of the actual pin states. If port 3 is read while PCR3 bits are cleared to 0, the pin states are read.
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Section 8 I/O Ports
Upon reset, PDR3 is initialized to H'00. Port Control Register 3 (PCR3)
Bit Initial value Read/Write 7 0 6 0 5 0 4 0 3 0 2 PCR32 0 W 1 PCR31 0 W 0 PCR30 0 W
PCR3 is an 8-bit register for controlling whether each of the port 3 pins P32 to P30 functions as an input pin or output pin. Setting a PCR3 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR3 and in PDR3 are valid only when the corresponding pin is designated in PMR3 as a general I/O pin. Upon reset, PCR3 is initialized to H'00. PCR3 is a write-only register, which is always read as all 1s. Port Pull-Up Control Register 3 (PUCR3)
Bit Initial value Read/Write Note: * 7 0* 6 0* 5 0* 4 0* 3 0* 2 0 R/W 1 0 R/W 0 0 R/W
PUCR32 PUCR31 PUCR30
Bits 7 to 3 are reserved; they are always read as 0 and cannot be modified.
PUCR3 controls whether the MOS pull-up of each of the port 3 pins P32 to P30 is on or off. When a PCR3 bit is cleared to 0, setting the corresponding PUCR3 bit to 1 turns on the MOS pull-up for the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up. Upon reset, PUCR3 is initialized to H'00. Port Mode Register 3 (PMR3)
Bit Initial value Read/Write 7 0 6 0 5 0 4 0 3 0 2 SO1 0 R/W 1 SI1 0 R/W 0 SCK1 0 R/W
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Section 8 I/O Ports
PMR3 is an 8-bit read/write register, controlling the selection of pin functions for port 3 pins. Upon reset, PMR3 is initialized to H'00. Bits 7 to 3 Reserved Bits: Bits 7 to 3 are reserved: they are always read as 0 and cannot be modified. Bit 2 P32/SO1 Pin Function Switch (SO1): This bit selects whether pin P32/SO1 is used as P32 or as SO1.
Bit 2: SO1 0 1 Description Functions as P32 I/O pin Functions as SO1 output pin (initial value)
Bit 1 P31/SI1 Pin Function Switch (SI1): This bit selects whether pin P31/SI1 is used as P31 or as SI1.
Bit 1: SI1 0 1 Description Functions as P31 I/O pin Functions as SI1 input pin (initial value)
Bit 0 P30/SCK1 Pin Function Switch (SCK1): This bit selects whether pin P30/SCK1 is used as P30 or as SCK1.
Bit 0: SCK1 0 1 Description Functions as P30 I/O pin Functions as SCK1 I/O pin (initial value)
Port Mode Register 7 (PMR7)
Bit Initial value Read/Write 7 1 6 1 5 1 4 1 3 1 2 TXD 0 R/W 1 0 0 POF1 0 R/W
PMR7 is an 8-bit read/write register that turns the PMOS transistors of pins and P32/SO1 on and off. Upon reset, PMR7 is initialized to H'F8.
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Section 8 I/O Ports
Bits 7 to 3 Reserved Bits: Bits 7 to 3 are reserved; they are always read as 1, and cannot be modified. Bit 2 P22/TXD Pin Function Switch (TXD): Bit 2 selects whether pin P22/TXD is used as P22 or as TXD.
Bit 2: TXD 0 1 Description Functions as P22 I/O pin Functions as TXD output pin (initial value)
Bit 1 Reserved Bit: Bit 1 is reserved: it is always read as 0 and cannot be modified. Bit 0 P32/SO1 Pin PMOS Control (POF1): This bit controls the PMOS transistor in the P32/SO1 pin output buffer.
Bit 0: POF1 0 1 Description CMOS output NMOS open-drain output (initial value)
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Section 8 I/O Ports
8.4.3
Pin Functions
Table 8.9 shows the port 3 pin functions. Table 8.9
Pin P32/SO1
Port 3 Pin Functions
Pin Functions and Selection Method The pin function depends on bit SO1 in PMR3 and bit PCR32 in PCR3. SO1 PCR32 Pin function 0 0 1 P32 input pin P32 output pin 1 * SO1 output pin
P31/SI1
The pin function depends on bit SI1 in PMR3 and bit PCR31 in PCR3. SI1 PCR31 Pin function 0 0 1 P31 input pin P31 output pin 1 * SI1 input pin
P30/SCK1
The pin function depends on bit SCK1 in PMR3, bit CKS3 in SCR1, and bit PCR30 in PCR3. SCK1 CKS3 PCR30 Pin function 0 0 * 1 P30 input pin P30 output pin 0 * 1 1 *
SCK1 output SCK1 input pin pin
Legend: * Don't care
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Section 8 I/O Ports
8.4.4
Pin States
Table 8.10 shows the port 3 pin states in each operating mode. Table 8.10 Port 3 Pin States
Pins P32/SO1 P31/SI1 P30/SCK1 Note: * Reset Highimpedance Sleep Retains previous state Subsleep Retains previous state Standby Watch Subactive Active
Retains Functional Functional Highimpedance* previous state
A high-level signal is output when the MOS pull-up is in the on state.
8.4.5
MOS Input Pull-Up
Port 3 has a built-in MOS input pull-up function that can be controlled by software. When a PCR3 bit is cleared to 0, setting the corresponding PUCR3 bit to 1 turns on the MOS pull-up for that pin. The MOS pull-up function is in the off state after a reset.
PCR3n PUCR3n MOS input pull-up Legend: * Don't care Note: n = 2 to 0 0 Off 0 1 On 1 * Off
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Section 8 I/O Ports
8.5
8.5.1
Port 5
Overview
Port 5 is an 8-bit I/O port, configured as shown in figure 8.4.
P57/INT7 P56/INT6/TMIB P55/INT5/ADTRG Port 5 P54/INT4 P53/INT3 P52/INT2 P51/INT1 P50/INT0
Figure 8.4 Port 5 Pin Configuration 8.5.2 Register Configuration and Description
Table 8.11 shows the port 5 register configuration. Table 8.11 Port 5 Registers
Name Port data register 5 Port control register 5 Port pull-up control register 5 Abbr. PDR5 PCR5 PUCR5 R/W R/W W R/W Initial Value H'00 H'00 H'00 Address H'FFD8 H'FFE8 H'FFEF
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Section 8 I/O Ports
Port Data Register 5 (PDR5)
Bit Initial value Read/Write 7 P57 0 R/W 6 P56 0 R/W 5 P55 0 R/W 4 P54 0 R/W 3 P53 0 R/W 2 P52 0 R/W 1 P51 0 R/W 0 P50 0 R/W
PDR5 is an 8-bit register that stores data for port 5 pins P57 to P50. If port 5 is read while PCR5 bits are set to 1, the values stored in PDR5 are read, regardless of the actual pin states. If port 5 is read while PCR5 bits are cleared to 0, the pin states are read. Upon reset, PDR5 is initialized to H'00. Port Control Register 5 (PCR5)
Bit Initial value Read/Write 7 PCR57 0 W 6 PCR56 0 W 5 PCR55 0 W 4 PCR54 0 W 3 PCR53 0 W 2 PCR52 0 W 1 PCR51 0 W 0 PCR50 0 W
PCR5 is an 8-bit register for controlling whether each of the port 5 pins P57 to P50 functions as an input pin or output pin. Setting a PCR5 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. Upon reset, PCR5 is initialized to H'00. PCR5 is a write-only register, which is always read as all 1s. Port Pull-Up Control Register 5 (PUCR5)
Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
PUCR57 PUCR56 PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50
PUCR5 controls whether the MOS pull-up of each port 5 pin is on or off. When a PCR5 bit is cleared to 0, setting the corresponding PUCR5 bit to 1 turns on the MOS pull-up for the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up. Upon reset, PUCR5 is initialized to H'00.
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Section 8 I/O Ports
8.5.3
Pin Functions
Table 8.12 shows the port 5 pin functions. Table 8.12 Port 5 Pin Functions
Pin P57/INT7 Pin Functions and Selection Method The pin function depends on bit PCR57 in PCR5. PCR57 Pin function 0 P57 input pin INT7 input pin P56/INT6/TMIB The pin function depends on bit PCR56 in PCR5. PCR56 Pin function 0 P56 input pin 1 P56 output pin 1 P57 output pin
INT6 input pin and TMIB input pin P55/INT5/ ADTRG The pin function depends on bit PCR55 in PCR5. PCR55 Pin function 0 P55 input pin 1 P55 output pin
INT5 input pin and ADTRG input pin P54/INT4 to P50/INT0 The pin function depends on bit PCR5n in PCR5. (n = 4 to 0) PCR5n Pin function 0 P5n input pin INTn input pin 1 P5n output pin
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Section 8 I/O Ports
8.5.4
Pin States
Table 8.13 shows the port 5 pin states in each operating mode. Table 8.13 Port 5 Pin States
Pins P57/INT7 to P50/INT0 Note: * Reset Sleep Subsleep Retains previous state Standby Watch Subactive Active
HighRetains impedance previous state
Retains Functional Functional Highimpedance* previous state
A high-level signal is output when the MOS pull-up is in the on state.
8.5.5
MOS Input Pull-Up
Port 5 has a built-in MOS input pull-up function that can be controlled by software. When a PCR5 bit is cleared to 0, setting the corresponding PUCR5 bit to 1 turns on the MOS pull-up for that pin. The MOS pull-up function is in the off state after a reset.
PCR5n PUCR5n MOS input pull-up Legend: * Don't care Note: n = 7 to 0 0 Off 0 1 On 1 * Off
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Section 8 I/O Ports
8.6
8.6.1
Port 6
Overview
Port 6 is an 8-bit large-current I/O port, with a maximum sink current of 10 mA. The port 6 pin configuration is shown in figure 8.5.
P67 P66 P65 Port 6 P64 P63 P62 P61 P60
Figure 8.5 Port 6 Pin Configuration 8.6.2 Register Configuration and Description
Table 8.14 shows the port 6 register configuration. Table 8.14 Port 6 Registers
Name Port data register 6 Port control register 6 Abbr. PDR6 PCR6 R/W R/W W Initial Value H'00 H'00 Address H'FFD9 H'FFE9
Port Data Register 6 (PDR6)
Bit Initial value Read/Write 7 P67 0 R/W 6 P66 0 R/W 5 P65 0 R/W 4 P64 0 R/W 3 P63 0 R/W 2 P62 0 R/W 1 P61 0 R/W 0 P60 0 R/W
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Section 8 I/O Ports
PDR6 is an 8-bit register that stores data for port 6 pins P67 to P60. When a bit in PCR6 is set to 1, if port 6 is read the value of the corresponding PDR6 bit is returned directly regardless of the pin state. When a bit in PCR6 is cleared to 0, if port 6 is read the corresponding pin state is read. Upon reset, PDR6 is initialized to H'00. Port Control Register 6 (PCR6)
Bit Initial value Read/Write 7 PCR67 0 W 6 PCR66 0 W 5 PCR65 0 W 4 PCR64 0 W 3 PCR63 0 W 2 PCR62 0 W 1 PCR61 0 W 0 PCR60 0 W
PCR6 is an 8-bit register for controlling whether each of the port 6 pins P67 to P60 functions as an input pin or output pin. When a bit in PCR6 is set to 1, the corresponding pin of P67 to P60 becomes an output pin. Upon reset, PCR6 is initialized to H'00. PCR6 is a write-only register, which always reads all 1s. 8.6.3 Pin Functions
Table 8.15 shows the port 6 pin functions. Table 8.15 Port 6 Pin Functions
Pin P67 to P60 Pin Functions and Selection Method The pin function depends on bit PCR6n in PCR6 (n = 7 to 0) PCR6n Pin function 0 P6n input pin 1 P6n output pin
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Section 8 I/O Ports
8.6.4
Pin States
Table 8.16 shows the port 6 pin states in each operating mode. Table 8.16 Port 6 Pin States
Pins P67 toP60 Reset Sleep Subsleep Standby Watch Subactive Active
HighRetains Retains impedance previous previous state state
Retains Functional Functional Highimpedance* previous state
Note:
*
A high-level signal is output when the MOS pull-up is in the on state.
8.7
8.7.1
Port 7
Overview
Port 7 is a 8-bit I/O port, configured as shown in figure 8.6.
P77 P76/TMOV Port 7 P75/TMCIV P74/TMRIV P73
Figure 8.6 Port 7 Pin Configuration 8.7.2 Register Configuration and Description
Table 8.17 shows the port 7 register configuration. Table 8.17 Port 7 Registers
Name Port data register 7 Port control register 7 Abbr. PDR7 PCR7 R/W R/W W Initial Value H'00 H'00 Address H'FFDA H'FFEA
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Section 8 I/O Ports
Port Data Register 7 (PDR7)
Bit Initial value Read/Write Note: * 7 P77 0 R/W 6 P76 0 R/W 5 P75 0 R/W 4 P74 0 R/W 3 P73 0 R/W 2 0* 1 0* 0 0*
Bits 2 to 0 are reserved; they are always read as 0 and cannot be modified.
PDR7 is an 8-bit register that stores data for port 7 pins P77 to P73. If port 7 is read while PCR7 bits are set to 1, the values stored in PDR7 are read, regardless of the actual pin states. If port 7 is read while PCR7 bits are cleared to 0, the pin states are read. Upon reset, PDR7 is initialized to H'00. Port Control Register 7 (PCR7)
Bit Initial value Read/Write 7 PCR77 0 W 6 PCR76 0 W 5 PCR75 0 W 4 PCR74 0 W 3 PCR73 0 W 2 0 1 0 0 0
PCR7 is an 8-bit register for controlling whether each of the port 7 pins P77 to P73 functions as an input pin or output pin. Setting a PCR7 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. Upon reset, PCR7 is initialized to H'00. PCR7 is a write-only register, which always reads as all 1s.
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Section 8 I/O Ports
8.7.3
Pin Functions
Table 8.18 shows the port 7 pin functions. Table 8.18 Port 7 Pin Functions
Pin P77, P73 Pin Functions and Selection Method The pin function depends on bit PCR7n in PCR7. (n = 7 or 3) PCR7n Pin function P76/TMOV 0 P7n input pin 1 P7n output pin
The pin function depends on bit PCR76 in PCR7 and bits OS3 to OS0 in TCSRV. OS3 to OS0 PCR76 Pin function 0 0000 1 P76 input pin P76 output pin Not 0000 * TMOV output pin
P75/TMCIV
The pin function depends on bit PCR75 in PCR7. PCR75 Pin function 0 P75 input pin TMCIV input pin 1 P75 output pin
P74/TMRIV
The pin function depends on bit PCR74 in PCR7. PCR74 Pin function 0 P74 input pin TMRIV input pin 1 P74 output pin
Legend: * Don't care
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Section 8 I/O Ports
8.7.4
Pin States
Table 8.19 shows the port 7 pin states in each operating mode. Table 8.19 Port 7 Pin States
Pins P77 to P73 Reset Sleep Subsleep Standby Highimpedance Watch Subactive Active
HighRetains Retains impedance previous previous state state
Retains Functional Functional previous state
8.8
8.8.1
Port 8
Overview
Port 8 is an 8-bit I/O port configured as shown in figure 8.7.
P87 P86/FTID P85/FTIC Port 8 P84/FTIB P83//FTIA P82/FTOB P81/FTOA P80/FTCI
Figure 8.7 Port 8 Pin Configuration
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Section 8 I/O Ports
8.8.2
Register Configuration and Description
Table 8.20 shows the port 8 register configuration. Table 8.20 Port 8 Registers
Name Port data register 8 Port control register 8 Abbr. PDR8 PCR8 R/W R/W W Initial Value H'00 H'00 Address H'FFDB H'FFEB
Port Data Register 8 (PDR8)
Bit Initial value Read/Write 7 P87 0 R/W 6 P86 0 R/W 5 P85 0 R/W 4 P84 0 R/W 3 P83 0 R/W 2 P82 0 R/W 1 P81 0 R/W 0 P80 0 R/W
PDR8 is an 8-bit register that stores data for port 8 pins P87 to P80. If port 8 is read while PCR8 bits are set to 1, the values stored in PDR8 are read, regardless of the actual pin states. If port 8 is read while PCR8 bits are cleared to 0, the pin states are read. Upon reset, PDR8 is initialized to H'00. Port Control Register 8 (PCR8)
Bit Initial value Read/Write 7 PCR87 0 W 6 PCR86 0 W 5 PCR85 0 W 4 PCR84 0 W 3 PCR83 0 W 2 PCR82 0 W 1 PCR81 0 W 0 PCR80 0 W
PCR8 is an 8-bit register for controlling whether each of the port 8 pins P87 to P80 functions as an input or output pin. Setting a PCR8 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. Upon reset, PCR8 is initialized to H'00. PCR8 is a write-only register, which is always read as all 1s.
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Section 8 I/O Ports
8.8.3
Pin Functions
Table 8.21 shows the port 8 pin functions. Table 8.21 Port 8 Pin Functions
Pin P87 Pin Functions and Selection Method The pin function depends on bit PCR87 in PCR8. PCR87 Pin function P86/FTID 0 P87 input pin 1 P87 output pin
The pin function depends on bit PCR86 in PCR8. PCR86 Pin function 0 P86 input pin FTID input pin 1 P86 output pin
P85/FTIC
The pin function depends on bit PCR85 in PCR8. PCR85 Pin function 0 P85 input pin FTIC input pin 1 P85 output pin
P84/FTIB
The pin function depends on bit PCR84 in PCR8. PCR84 Pin function 0 P84 input pin FTIB input pin 1 P84 output pin
P83/FTIA
The pin function depends on bit PCR83 in PCR8. PCR83 Pin function 0 P83 input pin FTIA input pin 1 P83 output pin
P82/FTOB
The pin function depends on bit PCR82 in PCR8 and bit OEB in TOCR. OEB PCR82 Pin function 0 0 1 P82 input pin P82 output pin 1 * FTOB output pin
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Section 8 I/O Ports Pin P81/FTOA Pin Functions and Selection Method The pin function depends on bit PCR81 in PCR8 and bit OEA in TOCR. OEA PCR81 Pin function P80/FTCI 0 0 1 P81 input pin P81 output pin 1 * FTOA output pin
The pin function depends on bit PCR80 in PCR8. PCR80 Pin function 0 P80 input pin FTCI input pin 1 P80 output pin
Legend: * Don't care
8.8.4
Pin States
Table 8.22 shows the port 8 pin states in each operating mode. Table 8.22
Pins
Port 8 Pin States
Reset Sleep Subsleep Standby Highimpedance Watch Subactive Active
Retains Retains P87 to P80/FTCI Highimpedance previous previous state state
Retains Functional Functional previous state
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Section 8 I/O Ports
8.9
8.9.1
Port 9
Overview
Port 9 is a 5-bit I/O port, configured as shown in figure 8.8.
P9 4 P9 3 Port 9 P9 2 P9 1 P9 0 *
Note: * There is no P90 function in the flash memory version since P90 is used as the FVPP pin.
Figure 8.8 Port 9 Pin Configuration 8.9.2 Register Configuration and Description
Table 8.23 shows the port 9 register configuration. Table 8.23 Port 9 Registers
Name Port data register 9 Port control register 9 Abbr. PDR9 PCR9 R/W R/W W Initial Value H'C0 H'C0 Address H'FFDC H'FFEC
Port Data Register 9 (PDR9)
Bit Initial value Read/Write 7 1 1* 6 1 1* 5 2 0* 4 P94 0 R/W 3 P93 0 R/W 2 P92 0 R/W 1 P91 0 R/W 0 P90* 0 R/W
3
Notes: 1. Bits 7 to 6 are reserved; they are always read as 1 and cannot be modified. 2. Bit 5 is reserved; it is always read as 0 and cannot be modified. 3. In the on-chip flash memory version, this bit is always read as 0 and cannot be modified. Rev. 6.00 Sep 12, 2006 page 199 of 526 REJ09B0326-0600
Section 8 I/O Ports
PDR9 is an 8-bit register that stores data for port 9 pins P94 to P90. If port 9 is read while PCR9 bits are set to 1, the values stored in PDR9 are read, regardless of the actual pin states. If port 9 is read while PCR9 bits are cleared to 0, the pin states are read. Upon reset, PDR9 is initialized to H'C0. Port Control Register 9 (PCR9)
Bit Initial value Read/Write 7 0 6 0 5 0 4 PCR94 0 W 3 PCR93 0 W 2 PCR92 0 W 1 PCR91 0 W 0 PCR90 0 W
PCR9 controls whether each of the port 9 pins P94 to P90 functions as an input pin or output pin. Setting a PCR9 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. Upon reset, PCR9 is initialized to H'C0. PCR9 is a write-only register, which is always reads as all 1. 8.9.3 Pin Functions
Table 8.24 shows the port 9 pin functions. Table 8.24 Port 9 Pin Functions
Pin P9n Pin Functions and Selection Method The pin function depends on bit PCR9n in PCR9. (n = 4 to 0) PCR9n Pin function 0 P9n input pin 1 P9n output pin
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Section 8 I/O Ports
8.9.4
Pin States
Table 8.25 shows the port 9 pin states in each operating mode. Table 8.25 Port 9 Pin States
Pins P94 to P90 Reset Sleep Subsleep Standby Highimpedance Watch Subactive Active
HighRetains Retains impedance previous previous state state
Retains Functional Functional previous state
8.10
8.10.1
Port B
Overview
Port B is an 8-bit input-only port, configured as shown in figure 8.9.
PB7 /AN 7 PB6 /AN 6 PB5 /AN 5 Port B PB4 /AN 4 PB3 /AN 3 PB2 /AN 2 PB1 /AN 1 PB0 /AN 0
Figure 8.9 Port B Pin Configuration 8.10.2 Register Configuration and Description
Table 8.26 shows the port B register configuration. Table 8.26 Port B Register
Name Port data register B Abbr. PDRB R/W R Address H'FFDD Rev. 6.00 Sep 12, 2006 page 201 of 526 REJ09B0326-0600
Section 8 I/O Ports
Port Data Register B (PDRB)
Bit 7 PB7 Read/Write R 6 PB6 R 5 PB5 R 4 PB4 R 3 PB3 R 2 PB2 R 1 PB1 R 0 PB0 R
Reading PDRB always gives the pin states. However, if a port B pin is selected as an analog input channel for the A/D converter by AMR bits CH3 to CH0, that pin reads 0 regardless of the input voltage. 8.10.3 Pin Functions
Table 8.27 shows the port B pin functions. Table 8.27 Port B Pin Functions
Pin PBn/ANn Pin Functions and Selection Method Always as below. (n = 7 to 0) Pin function PBn input pin or ANn input pin
8.10.4
Pin States
Table 8.28 shows the port B pin states in each operating mode. Table 8.28 Port B Pin States
Pins PBn/ANn Reset Sleep Subsleep Standby Watch Subactive Active
HighHighHighHighHighHighHighimpedance impedance impedance impedance impedance impedance impedance (n = 7 to 0)
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Section 9 Timers
Section 9 Timers
9.1 Overview
The H8/3644 Group provides five timers: timers A, B1, V, X, and a watchdog timer. The functions of these timers are outlined in table 9.1. Table 9.1
Name Timer A
Timer Functions
Functions 8-bit timer * * Interval function Time base /8 to /8192 (8 choices) W /128 (choice of 4 overflow periods) /4 to /32 W /4 to W /32 (8 choices) /4 to /8192 (7 choices) /4 to /128 (6 choices) TMOW Internal Clock Event Input Pin Waveform Output Pin Remarks
*
Clock output
Timer B1
Timer V
* * * * * * * *
Timer X
* *
* * * Watchdog * timer
8-bit timer Interval timer Event counter 8-bit timer Event counter Output control by dual compare match Counter clearing option Count-up start by external trigger input can be specified 16-bit free-running timer 2 output compare channels 4 input capture channels Counter clearing option Event counter Reset signal generated when 8-bit counter overflows
TMIB
TMCIV
TMOV
/2 to /32 (3 choices)
FTCI FTIA FTIB FTIC FTID
FTOA FTOB
/8192
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Section 9 Timers
9.2
9.2.1
Timer A
Overview
Timer A is an 8-bit timer with interval timing and real-time clock time-base functions. The clock time-base function is available when a 32.768-kHz crystal resonator is connected. A clock signal divided from 32.768 kHz or from the system clock can be output at the TMOW pin. Features Features of timer A are given below. * Choice of eight internal clock sources (/8192, /4096, /2048, /512, /256, /128, /32, /8). * Choice of four overflow periods (1 s, 0.5 s, 0.25 s, 31.25 ms) when timer A is used as a clock time base (using a 32.768 kHz crystal resonator). * An interrupt is requested when the counter overflows. * Any of eight clock signals can be output from pin TMOW: 32.768 kHz divided by 32, 16, 8, or 4 (1 kHz, 2 kHz, 4 kHz, 8 kHz), or the system clock divided by 32, 16, 8, or 4.
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Section 9 Timers
Block Diagram Figure 9.1 shows a block diagram of timer A.
W
1/4
W /4 W/32 W/16 W/8 W/4
PSW
TMA
W/128 TCA /8192, /4096, /2048, /512, /256, /128, /32, /8 PSS
/128* /256*
TMOW /32 /16 /8 /4
/64* /8*
IRRTA
Legend:
TMA: TCA: IRRTA: PSW: PSS: Timer mode register A Timer counter A Timer A overflow interrupt request flag Prescaler W Prescaler S
Note: * Can be selected only when the prescaler W output (W/128) is used as the TCA input clock.
Figure 9.1 Block Diagram of Timer A Pin Configuration Table 9.2 shows the timer A pin configuration. Table 9.2
Name Clock output
Pin Configuration
Abbr. TMOW I/O Output Function Output of waveform generated by timer A output circuit
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Internal data bus
Section 9 Timers
Register Configuration Table 9.3 shows the register configuration of timer A. Table 9.3
Name Timer mode register A Timer counter A
Timer A Registers
Abbr. TMA TCA R/W R/W R Initial Value H'10 H'00 Address H'FFB0 H'FFB1
9.2.2
Register Descriptions
Timer Mode Register A (TMA)
Bit Initial value Read/Write 7 TMA7 0 R/W 6 TMA6 0 R/W 5 TMA5 0 R/W 4 1 3 TMA3 0 R/W 2 TMA2 0 R/W 1 TMA1 0 R/W 0 TMA0 0 R/W
TMA is an 8-bit read/write register for selecting the prescaler, input clock, and output clock. Upon reset, TMA is initialized to H'10. Bits 7 to 5Clock Output Select (TMA7 to TMA5): Bits 7 to 5 choose which of eight clock signals is output at the TMOW pin. The system clock divided by 32, 16, 8, or 4 can be output in active mode and sleep mode. A 32.768 kHz signal divided by 32, 16, 8, or 4 can be output in active mode, sleep mode, and subactive mode.
Bit 7: TMA7 0 Bit 6: TMA6 0 1 1 0 1 Bit 5: TMA5 0 1 0 1 0 1 0 1 Clock Output /32 /16 /8 /4 W /32 W /16 W /8 W /4 (initial value)
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Section 9 Timers
Bit 4Reserved Bit: Bit 4 is reserved; it is always read as 1, and cannot be modified. Bits 3 to 0Internal Clock Select (TMA3 to TMA0): Bits 3 to 0 select the clock input to TCA. The selection is made as follows.
Description Bit 3: TMA3 0 Bit 2: TMA2 0 Bit 1: TMA1 0 1 1 0 1 1 0 0 1 1 0 1 Bit 0: TMA0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Prescaler and Divider Ratio or Overflow Period PSS, /8192 PSS, /4096 PSS, /2048 PSS, /512 PSS, /256 PSS, /128 PSS, /32 PSS, /8 PSW, 1 s PSW, 0.5 s PSW, 0.25 s PSW, 0.03125 s PSW and TCA are reset Clock time base (initial value) Function Interval timer
Timer Counter A (TCA)
Bit Initial value Read/Write 7 TCA7 0 R 6 TCA6 0 R 5 TCA5 0 R 4 TCA4 0 R 3 TCA3 0 R 2 TCA2 0 R 1 TCA1 0 R 0 TCA0 0 R
TCA is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock source for input to this counter is selected by bits TMA3 to TMA0 in timer mode register A (TMA). TCA values can be read by the CPU in active mode, but cannot be read in subactive mode. When TCA overflows, the IRRTA bit in interrupt request register 1 (IRR1) is set to 1.
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Section 9 Timers
TCA is cleared by setting bits TMA3 and TMA2 of TMA to 11. Upon reset, TCA is initialized to H'00. 9.2.3 Timer Operation
Interval Timer Operation: When bit TMA3 in timer mode register A (TMA) is cleared to 0, timer A functions as an 8-bit interval timer. Upon reset, TCA is cleared to H'00 and bit TMA3 is cleared to 0, so up-counting and interval timing resume immediately. The clock input to timer A is selected by bits TMA2 to TMA0 in TMA; any of eight internal clock signals output by prescaler S can be selected. After the count value in TCA reaches H'FF, the next clock signal input causes timer A to overflow, setting bit IRRTA to 1 in interrupt request register 1 (IRR1). If IENTA = 1 in interrupt enable register 1 (IENR1), a CPU interrupt is requested.* At overflow, TCA returns to H'00 and starts counting up again. In this mode timer A functions as an interval timer that generates an overflow output at intervals of 256 input clock pulses. Note: * For details on interrupts, see section 3.3, Interrupts. Real-Time Clock Time Base Operation: When bit TMA3 in TMA is set to 1, timer A functions as a real-time clock time base by counting clock signals output by prescaler W. The overflow period of timer A is set by bits TMA1 and TMA0 in TMA. A choice of four periods is available. In time base operation (TMA3 = 1), setting bit TMA2 to 1 clears both TCA and prescaler W to their initial values of H'00. Clock Output: Setting bit TMOW in port mode register 1 (PMR1) to 1 causes a clock signal to be output at pin TMOW. Eight different clock output signals can be selected by means of bits TMA7 to TMA5 in TMA. The system clock divided by 32, 16, 8, or 4 can be output in active mode and sleep mode. A 32.768 kHz signal divided by 32, 16, 8, or 4 can be output in active mode, sleep mode, and subactive mode.
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Section 9 Timers
9.2.4
Timer A Operation States
Table 9.4 summarizes the timer A operation states. Table 9.4 Timer A Operation States
Reset Active Reset Reset Reset Sleep Watch Subactive Halted Subsleep Halted Standby Halted
Operation Mode TCA Interval Clock time base TMA
Functions Functions Halted
Functions Functions Functions Functions Functions Halted Functions Retained Retained Functions Retained Retained
Note: When the real-time clock time base function is selected as the internal clock of TCA in active mode or sleep mode, the internal clock is not synchronous with the system clock, so it is synchronized by a synchronizing circuit. This may result in a maximum error of 1/ (s) in the count cycle.
9.3
9.3.1
Timer B1
Overview
Timer B1 is an 8-bit timer that increments each time a clock pulse is input. This timer has two operation modes, interval and auto reload. Features Features of timer B1 are given below. * Choice of seven internal clock sources (/8192, /2048, /512, /256, /64, /16, /4) or an external clock (can be used to count external events). * An interrupt is requested when the counter overflows.
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Section 9 Timers
Block Diagram Figure 9.2 shows a block diagram of timer B1.
TMB1
PSS
TCB1
TMIB
TLB1
Legend:
TMB1: Timer mode register B1 TCB1: Timer counter B1 TLB1: Timer load register B1 IRRTB1: Timer B1 interrupt request flag PSS: Prescaler S
Figure 9.2 Block Diagram of Timer B1 Pin Configuration Table 9.5 shows the timer B1 pin configuration. Table 9.5
Name Timer B1 event input
Pin Configuration
Abbr. TMIB I/O Input Function Event input to TCB1
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Internal data bus
IRRTB1
Section 9 Timers
Register Configuration Table 9.6 shows the register configuration of timer B1. Table 9.6
Name Timer mode register B1 Timer counter B1 Timer load register B1
Timer B1 Registers
Abbr. TMB1 TCB1 TLB1 R/W R/W R W Initial Value H'78 H'00 H'00 Address H'FFB2 H'FFB3 H'FFB3
9.3.2
Register Descriptions
Timer Mode Register B1 (TMB1)
Bit Initial value Read/Write 7 TMB17 0 R/W 6 1 5 1 4 1 3 1 2 TMB12 0 R/W 1 TMB11 0 R/W 0 TMB10 0 R/W
TMB1 is an 8-bit read/write register for selecting the auto-reload function and input clock. Upon reset, TMB1 is initialized to H'78. Bit 7Auto-Reload Function Select (TMB17): Bit 7 selects whether timer B1 is used as an interval timer or auto-reload timer.
Bit 7: TMB17 0 1 Description Interval timer function selected Auto-reload function selected (initial value)
Bits 6 to 3Reserved Bits: Bits 6 to 3 are reserved; they are always read as 1, and cannot be modified.
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Section 9 Timers
Bits 2 to 0Clock Select (TMB12 to TMB10): Bits 2 to 0 select the clock input to TCB1. For external event counting, either the rising or falling edge can be selected.
Bit 2: TMB12 0 Bit 1: TMB11 0 1 1 0 1 Note: * Bit 0: TMB10 0 1 0 1 0 1 0 1 Description Internal clock: /8192 Internal clock: /2048 Internal clock: /512 Internal clock: /256 Internal clock: /64 Internal clock: /16 Internal clock: /4 External event (TMIB): rising or falling edge* (initial value)
The edge of the external event signal is selected by bit INTEG6 in interrupt edge select register 2 (IEGR2). See section 3.3.2, Interrupt Control Registers, for details.
Timer Counter B1 (TCB1)
Bit Initial value Read/Write 7 TCB17 0 R 6 TCB16 0 R 5 TCB15 0 R 4 TCB14 0 R 3 TCB13 0 R 2 TCB12 0 R 1 TCB11 0 R 0 TCB10 0 R
TCB1 is an 8-bit read-only up-counter, which is incremented by internal clock or external event input. The clock source for input to this counter is selected by bits TMB12 to TMB10 in timer mode register B1 (TMB1). TCB1 values can be read by the CPU at any time. When TCB1 overflows from H'FF to H'00 or to the value set in TLB1, the IRRTB1 bit in IRR1 is set to 1. TCB1 is allocated to the same address as TLB1. Upon reset, TCB1 is initialized to H'00.
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Section 9 Timers
Timer Load Register B1 (TLB1)
Bit Initial value Read/Write 7 TLB17 0 W 6 TLB16 0 W 5 TLB15 0 W 4 TLB14 0 W 3 TLB13 0 W 2 TLB12 0 W 1 TLB11 0 W 0 TLB10 0 W
TLB1 is an 8-bit write-only register for setting the reload value of timer counter B1 (TCB1). When a reload value is set in TLB1, the same value is loaded into timer counter B1 (TCB1) as well, and TCB1 starts counting up from that value. When TCB1 overflows during operation in auto-reload mode, the TLB1 value is loaded into TCB1. Accordingly, overflow periods can be set within the range of 1 to 256 input clocks. The same address is allocated to TLB1 as to TCB1. Upon reset, TLB1 is initialized to H'00. 9.3.3 Timer Operation
Interval Timer Operation: When bit TMB17 in timer mode register B1 (TMB1) is cleared to 0, timer B1 functions as an 8-bit interval timer. Upon reset, TCB1 is cleared to H'00 and bit TMB17 is cleared to 0, so up-counting and interval timing resume immediately. The clock input to timer B1 is selected from seven internal clock signals output by prescaler S, or an external clock input at pin TMIB. The selection is made by bits TMB12 to TMB10 of TMB1. After the count value in TCB1 reaches H'FF, the next clock signal input causes timer B1 to overflow, setting bit IRRTB1 to 1 in interrupt request register 1 (IRR1). If IENTB1 = 1 in interrupt enable register 1 (IENR1), a CPU interrupt is requested.* At overflow, TCB1 returns to H'00 and starts counting up again. During interval timer operation (TMB17 = 0), when a value is set in timer load register B1 (TLB1), the same value is set in TCB1. Note: * For details on interrupts, see section 3.3, Interrupts.
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Section 9 Timers
Auto-Reload Timer Operation: Setting bit TMB17 in TMB1 to 1 causes timer B1 to function as an 8-bit auto-reload timer. When a reload value is set in TLB1, the same value is loaded into TCB1, becoming the value from which TCB1 starts its count. After the count value in TCB1 reaches H'FF, the next clock signal input causes timer B1 to overflow. The TLB1 value is then loaded into TCB1, and the count continues from that value. The overflow period can be set within a range from 1 to 256 input clocks, depending on the TLB1 value. The clock sources and interrupts in auto-reload mode are the same as in interval mode. In auto-reload mode (TMB17 = 1), when a new value is set in TLB1, the TLB1 value is also set in TCB1. Event Counter Operation: Timer B1 can operate as an event counter, counting rising or falling edges of an external event signal input at pin TMIB. External event counting is selected by setting bits TMB12 to TMB10 in timer mode register B1 (TMB1) to all 1s (111). When timer B1 is used to count external event input, bit INTEN6 in IENR3 should be cleared to 0 to disable INT6 interrupt requests. 9.3.4 Timer B1 Operation States
Table 9.7 summarizes the timer B1 operation states. Table 9.7 Timer B1 Operation States
Reset Reset Reset Reset Active Functions Functions Functions Sleep Functions Functions Retained Watch Halted Halted Retained Subactive Halted Halted Subsleep Halted Halted Standby Halted Halted
Operation Mode TCB1 Interval Auto reload TMB1
Retained Retained Retained
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Section 9 Timers
9.4
9.4.1
Timer V
Overview
Timer V is an 8-bit timer based on an 8-bit counter. Timer V counts external events. Also compare match signals can be used to reset the counter, request an interrupt, or output a pulse signal with an arbitrary duty cycle. Counting can be initiated by a trigger input at the TRGV pin, enabling pulse output control to be synchronized to the trigger, with an arbitrary delay from the trigger input. Features Features of timer V are given below. * Choice of six internal clock sources (/128, /64, /32, /16, /8, /4) or an external clock (can be used as an external event counter). * Counter can be cleared by compare match A or B, or by an external reset signal. If the count stop function is selected, the counter can be halted when cleared. * Timer output is controlled by two independent compare match signals, enabling pulse output with an arbitrary duty cycle, PWM output, and other applications. * Three interrupt sources: two compare match, one overflow * Counting can be initiated by trigger input at the TRGV pin. The rising edge, falling edge, or both edges of the TRGV input can be selected.
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Section 9 Timers
Block Diagram Figure 9.3 shows a block diagram of timer V.
TCRV1
TCORB TRGV Trigger control Comparator
TMCIV
Clock select
TCNTV
Internal data bus
Comparator PSS TCORA
TMRIV
Clear control
TCRV0 Interrupt request control
TMOV
Output control
TCSRV CMIA CMIB OVI
Legend:
TCORA: TCORB: TCNTV: TCSRV: TCRV0: TCRV1: PSS: CMIA: CMIB: OVI: Time constant register A Time constant register B Timer counter V Timer control/status register V Timer control register V0 Timer control register V1 Prescaler S Compare-match interrupt A Compare-match interrupt B Overflow interrupt
Figure 9.3 Block Diagram of Timer V
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Section 9 Timers
Pin Configuration Table 9.8 shows the timer V pin configuration. Table 9.8
Name Timer V output Timer V clock input Timer V reset input Trigger input
Pin Configuration
Abbr. TMOV TMCIV TMRIV TRGV I/O Output Input Input Input Function Timer V waveform output Clock input to TCNTV External input to reset TCNTV Trigger input to initiate counting
Register Configuration Table 9.9 shows the register configuration of timer V. Table 9.9
Name Timer control register V0 Timer control/status register V Time constant register A Time constant register B Timer counter V Timer control register V1 Note: *
Timer V Registers
Abbr. TCRV0 TCSRV TCORA TCORB TCNTV TCRV1 R/W R/W R/(W)* R/W R/W R/W R/W Initial Value H'00 H'10 H'FF H'FF H'00 H'E2 Address H'FFB8 H'FFB9 H'FFBA H'FFBB H'FFBC H'FFBD
Bits 7 to 5 can only be written with 0, for flag clearing.
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Section 9 Timers
9.4.2
Register Descriptions
Timer Counter V (TCNTV)
Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
TCNTV7 TCNTV6 TCNTV5 TCNTV4 TCNTV3 TCNTV2 TCNTV1 TCNTV0
TCNTV is an 8-bit read/write up-counter which is incremented by internal or external clock input. The clock source is selected by bits CKS2 to CKS0 in TCRV0. The TCNTV value can be read and written by the CPU at any time. TCNTV can be cleared by an external reset signal, or by compare match A or B. The clearing signal is selected by bits CCLR1 and CCLR0 in TCRV0. When TCNTV overflows from H'FF to H'00, OVF is set to 1 in TCSRV. TCNTV is initialized to H'00 upon reset and in standby mode, watch mode, subsleep mode, and subactive mode. Time Constant Registers A and B (TCORA, TCORB)
Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W n = A or B
TCORn7 TCORn6 TCORn5 TCORn4 TCORn3 TCORn2 TCORn1 TCORn0
TCORA and TCORB are 8-bit read/write registers. TCORA and TCNTV are compared at all times, except during the T3 state of a TCORA write cycle. When the TCORA and TCNTV contents match, CMFA is set to 1 in TCSRV. If CMIEA is also set to 1 in TCRV0, a CPU interrupt is requested. Timer output from the TMOV pin can be controlled by a signal resulting from compare match, according to the settings of bits OS3 to OS0 in TCSRV. TCORA is initialized to H'FF upon reset and in standby mode, watch mode, subsleep mode, and subactive mode. TCORB is similar to TCORA.
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Section 9 Timers
Timer Control Register V0 (TCRV0)
Bit Initial value Read/Write 7 CMIEB 0 R/W 6 CMIEA 0 R/W 5 OVIE 0 R/W 4 CCLR1 0 R/W 3 CCLR0 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W
TCRV0 is an 8-bit read/write register that selects the TCNTV input clock, controls the clearing of TCNTV, and enables interrupts. TCRV0 is initialized to H'00 upon reset and in standby mode, watch mode, subsleep mode, and subactive mode. Bit 7Compare Match Interrupt Enable B (CMIEB): Bit 7 enables or disables the interrupt request (CMIB) generated from CMFB when CMFB is set to 1 in TCSRV.
Bit 7: CMIEB 0 1 Description Interrupt request (CMIB) from CMFB disabled Interrupt request (CMIB) from CMFB enabled (initial value)
Bit 6Compare Match Interrupt Enable A (CMIEA): Bit 6 enables or disables the interrupt request (CMIA) generated from CMFA when CMFA is set to 1 in TCSRV.
Bit 6: CMIEA 0 1 Description Interrupt request (CMIA) from CMFA disabled Interrupt request (CMIA) from CMFA enabled (initial value)
Bit 5Timer Overflow Interrupt Enable (OVIE): Bit 5 enables or disables the interrupt request (OVI) generated from OVF when OVF is set to 1 in TCSRV.
Bit 5: OVIE 0 1 Description Interrupt request (OVI) from OVF disabled Interrupt request (OVI) from OVF enabled (initial value)
Bits 4 and 3Counter Clear 1 and 0 (CCLR1, CCLR0): Bits 4 and 3 specify whether or not to clear TCNTV, and select compare match A or B or an external reset input. When clearing is specified, if TRGE is set to 1 in TCRV1, then when TCNTV is cleared it is also halted. Counting resumes when a trigger edge is input at the TRGV pin.
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Section 9 Timers
If TRGE is cleared to 0, after TCNTV is cleared it continues counting up.
Bit 4: CCLR1 0 1 Bit 3: CCLR0 0 1 0 1 Description Clearing is disabled Cleared by compare match A Cleared by compare match B Cleared by rising edge of external reset input (initial value)
Bits 2 to 0Clock Select 2 to 0 (CKS2 to CKS0): Bits 2 to 0 and bit ICKS0 in TCRV1 select the clock input to TCNTV. Six internal clock sources divided from the system clock () can be selected. The counter increments on the falling edge. If the external clock is selected, there is a further selection of incrementing on the rising edge, falling edge, or both edges. If TRGE is cleared to 0, after TCNTV is cleared it continues counting up.
TCRV0 Bit 2: CKS2 0 Bit 1: CKS1 0 Bit 0: CKS0 0 1 1 0 1 1 0 1 0 1 0 1 TCRV1 Bit 0: ICKS0 0 1 0 1 0 1 Description Clock input disabled Internal clock: /4, falling edge Internal clock: /8, falling edge Internal clock: /16, falling edge Internal clock: /32, falling edge Internal clock: /64, falling edge Internal clock: /128, falling edge Clock input disabled External clock: rising edge External clock: falling edge External clock: rising and falling edges (initial value)
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Section 9 Timers
Timer Control/Status Register V (TCSRV)
Bit Initial value Read/Write Note: * 7 CMFB 0 R/(W)* 6 CMFA 0 R/(W)* 5 OVF 0 R/(W)* 4 1 3 OS3 0 R/W 2 OS2 0 R/W 1 OS1 0 R/W 0 OS0 0 R/W
Bits 7 to 5 can be only written with 0, for flag clearing.
TCSRV is an 8-bit register that sets compare match flags and the timer overflow flag, and controls compare match output. TCSRV is initialized to H'10 upon reset and in standby mode, watch mode, subsleep mode, and subactive mode. Bit 7Compare Match Flag B (CMFB): Bit 7 is a status flag indicating that TCNTV has matched TCORB. This flag is set by hardware and cleared by software. It cannot be set by software.
Bit 7: CMFB 0 1 Description Clearing condition: After reading CMFB = 1, cleared by writing 0 to CMFB Setting condition: Set when the TCNTV value matches the TCORB value (initial value)
Bit 6Compare Match Flag A (CMFA): Bit 6 is a status flag indicating that TCNTV has matched TCORA. This flag is set by hardware and cleared by software. It cannot be set by software.
Bit 6: CMFA 0 1 Description Clearing condition: After reading CMFA = 1, cleared by writing 0 to CMFA Setting condition: Set when the TCNTV value matches the TCORA value (initial value)
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Bit 5Timer Overflow Flag (OVF): Bit 5 is a status flag indicating that TCNTV has overflowed from H'FF to H'00. This flag is set by hardware and cleared by software. It cannot be set by software.
Bit 5: OVF 0 1 Description Clearing condition: After reading OVF = 1, cleared by writing 0 to OVF Setting condition: Set when TCNTV overflows from H'FF to H'00 (initial value)
Bit 4Reserved Bit: Bit 4 is reserved; it is always read as 1, and cannot be modified. Bits 3 to 0Output Select 3 to 0 (OS3 to OS0): Bits 3 to 0 select the way in which the output level at the TMOV pin changes in response to compare match between TCNTV and TCORA or TCORB. OS3 and OS2 select the output level for compare match B. OS1 and OS0 select the output level for compare match A. The two levels can be controlled independently. If two compare matches occur simultaneously, any conflict between the settings is resolved according to the following priority order: toggle output > 1 output > 0 output. When OS3 to OS0 are all cleared to 0, timer output is disabled. After a reset, the timer output is 0 until the first compare match.
Bit 3: OS3 0 1 Bit 2: OS2 0 1 0 1 Bit 1: OS1 0 1 Bit 0: OS0 0 1 0 1 Description No change at compare match B 0 output at compare match B 1 output at compare match B Output toggles at compare match B Description No change at compare match A 0 output at compare match A 1 output at compare match A Output toggles at compare match A (initial value) (initial value)
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Timer Control Register V1 (TCRV1)
Bit Initial value Read/Write 7 1 6 1 5 1 4 TVEG1 0 R/W 3 TVEG0 0 R/W 2 TRGE 0 R/W 1 1 0 ICKS0 0 R/W
TCRV1 is an 8-bit read/write register that selects the valid edge at the TRGV pin, enables TRGV input, and selects the clock input to TCNTV. TCRV1 is initialized to H'E2 upon reset and in watch mode, subsleep mode, and subactive mode. Bits 7 to 5Reserved Bits: Bit 7 to 5 are reserved; they are always read as 1, and cannot be modified. Bits 4 and 3TRGV Input Edge Select (TVEG1, TVEG0): Bits 4 and 3 select the TRGV input edge.
Bit 4: TVEG1 0 1 Bit 3: TVEG0 0 1 0 1 Description TRGV trigger input is disabled Rising edge is selected Falling edge is selected Rising and falling edges are both selected (initial value)
Bit 2TRGV Input Enable (TRGE): Bit 2 enables TCNTV counting to be triggered by input at the TRGV pin, and enables TCNTV counting to be halted when TCNTV is cleared by compare match. TCNTV stops counting when TRGE is set to 1, then starts counting when the edge selected by bits TVEG1 and TVEG0 is input at the TRGV pin.
Bit 2: TRGE 0 1 Description TCNTV counting is not triggered by input at the TRGV pin, and does not stop when TCNTV is cleared by compare match (initial value) TCNTV counting is triggered by input at the TRGV pin, and stops when TCNTV is cleared by compare match
Bit 1Reserved Bit: Bit 1 is reserved; it is always read as 1, and cannot be modified. Bit 0Internal Clock Select 0 (ICKS0): Bit 0 and bits CKS2 to CKS0 in TCRV0 select the TCNTV clock source. For details see section 9.4.2, Register Descriptions.
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9.4.3
Timer Operation
Timer V Operation: A reset initializes TCNTV to H'00, TCORA and TCORB to H'FF, TCRV0 to H'00, TCSRV to H'10, and TCRV1 to H'E2. Timer V can be clocked by one of six internal clocks output from prescaler S, or an external clock, as selected by bits CKS2 to CKS0 in TCRV0 and bit ICKS0 in TCRV1. The valid edge or edges of the external clock can also be selected by CKS2 to CKS0. When the clock source is selected, TCNTV starts counting the selected clock input. The TCNTV contents are always compared with TCORA and TCORB. When a match occurs, the CMFA or CMFB bit is set to 1 in TCSRV. If CMIEA or CMIEB is set to 1 in TCRV0, a CPU interrupt is requested. At the same time, the output level selected by bits OS3 to OS0 in TCSRV is output from the TMOV pin. When TCNT overflows from H'FF to H'00, if OVIE is 1 in TCRV0, a CPU interrupt is requested. If bits CCLR1 and CCLR0 in TCRV0 are set to 01 (clear by compare match A) or 10 (clear by compare match B), TCNTV is cleared by the corresponding compare match. If these bits are set to 11, TCNTV is cleared by input of a rising edge at the TMRIV pin. When the counter clear event selected by bits CCLR1 and CCLR0 in TCRV0 occurs, TCNTV is cleared and the count-up is halted. TCNTV starts counting when the signal edge selected by bits TVEG1 and TVEG0 in TCRV1 is input at the TRGV pin.
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TCNTV Increment Timing: TCNTV is incremented by an input (internal or external) clock. * Internal clock One of six clocks (/128, /64, /32, /16, /8, /4) divided from the system clock () can be selected by bits CKS2 to CKS0 in TCRV0 and bit ICKS0 in TCRV1. Figure 9.4 shows the timing.
Internal clock
FRC input TCNTV input TCNTV
N-1
N
N-1
Figure 9.4 Increment Timing with Internal Clock * External clock Incrementation on the rising edge, falling edge, or both edges of the external clock can be selected by bits CKS2 to CKS0 in TCRV0. The external clock pulse width should be at least 1.5 system clocks () when a single edge is counted, and at least 2.5 system clocks when both edges are counted. Shorter pulses will not be counted correctly. Figure 9.5 shows the timing when both the rising and falling edges of the external clock are selected.
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TMCIV (external clock input pin) TCNTV input clock
TCNTV
N-1
N
N-1
Figure 9.5 Increment Timing with External Clock Overflow flag Set Timing: The overflow flag (OVF) is set to 1 when TCNTV overflows from H'FF to H'00. Figure 9.6 shows the timing.
TCNTV
H'FF
H'00
Overflow signal
Figure 9.6 OVF Set Timing
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Compare Match Flag set Timing: Compare match flag A or B (CMFA or CMFB) is set to 1 when TCNTV matches TCORA or TCORB. The internal compare-match signal is generated in the last state in which the values match (when TCNTV changes from the matching value to a new value). Accordingly, when TCNTV matches TCORA or TCORB, the compare match signal is not generated until the next clock input to TCNTV. Figure 9.7 shows the timing.
TCNTV
N
N+1
TCORA or TCORB Compare match signal
N
CMFA or CMFB
Figure 9.7 CMFA and CMFB Set Timing TMOV Output Timing: The TMOV output responds to compare match A or B by remaining unchanged, changing to 0, changing to 1, or toggling, as selected by bits OS3 to OS0 in TCSRV. Figure 9.8 shows the timing when the output is toggled by compare match A.
Compare match A signal Timer V output pin
Figure 9.8 TMOV Output Timing
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TCNTV Clear Timing by Compare Match: TCNTV can be cleared by compare match A or B, as selected by bits CCLR1 and CCLR0 in TCRV0. Figure 9.9 shows the timing.
Compare match A signal
TCNTV
N
H'00
Figure 9.9 Clear Timing by Compare Match TCNTV Clear Timing by TMRIV: TCNTV can be cleared by a rising edge at the TMRIV pin, as selected by bits CCLR1 and CCLR0 in TCRV0. A TMRIV input pulse width of at least 1.5 system clocks is necessary. Figure 9.10 shows the timing.
Compare match A signal
Timer V output pin
TCNTV
N-1
N
H'00
Figure 9.10 Clear Timing by TMRIV Input
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9.4.4
Timer V Operation Modes
Table 9.10 summarizes the timer V operation states. Table 9.10 Timer V Operation States
Operation Mode TCNTV TCRV0, TCRV1 TCORA, TCORB TCSRV Reset Reset Reset Reset Reset Active Functions Functions Functions Functions Sleep Functions Functions Functions Functions Watch Reset Reset Reset Reset Subactive Reset Reset Reset Reset Subsleep Reset Reset Reset Reset Standby Reset Reset Reset Reset
9.4.5
Interrupt Sources
Timer V has three interrupt sources: CMIA, CMIB, and OVI. Table 9.11 lists the interrupt sources and their vector address. Each interrupt source can be enabled or disabled by an interrupt enable bit in TCRV0. Although all three interrupts share the same vector, they have individual interrupt flags, so software can discriminate the interrupt source. Table 9.11 Timer V Interrupt Sources
Interrupt CMIA CMIB OVI Description Generated from CMFA Generated from CMFB Generated from OVF Vector Address H'0022
9.4.6
Application Examples
Pulse Output with Arbitrary Duty Cycle: Figure 9.11 shows an example of output of pulses with an arbitrary duty cycle. To set up this output: * Clear bit CCLR1 to 0 and set bit CCLR0 to 1 in TCRV0 so that TCNTV will be cleared by compare match with TCORA. * Set bits OS3 to OS0 to 0110 in TCSRV so that the output will go to 1 at compare match with TCORA and to 0 at compare match with TCORB. * Set bits CKS2 to CKS0 in TCRV0 and bit ICKS0 in TCRV1 to select the desired clock source.
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With these settings, a waveform is output without further software intervention, with a period determined by TCORA and a pulse width determined by TCORB.
TCNTV H'FF TCORA TCORB H'00 Counter cleared
TMOV
Figure 9.11 Pulse Output Example Single-Shot Output with Arbitrary Pulse Width and Delay from TRGV Input: The trigger function can be used to output a pulse with an arbitrary pulse width at an arbitrary delay from the TRGV input, as shown in figure 9.12. To set up this output: * Set bit CCLR1 to 1 and clear bit CCLR0 to 0 in TCRV0 so that TCNTV will be cleared by compare match with TCORB. * Set bits OS3 to OS0 to 0110 in TCSRV so that the output will go to 1 at compare match with TCORA and to 0 at compare match with TCORB. * Set bits TVEG1 and TVEG0 to 10 in TCRV1 and set TRGE to 1 to select the falling edge of the TRGV input. * Set bits CKS2 to CKS0 in TCRV0 and bit ICKS0 in TCRV1 to select the desired clock source.
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After these settings, a pulse waveform will be output without further software intervention, with a delay determined by TCORA from the TRGV input, and a pulse width determined by (TCORB - TCORA).
TCNTV Counter cleared TCORB TCORA H'00 TRGV
H'FF
TMOV Compare match A Compare match B clears TCNTV and halts count-up Compare match A Compare match B clears TCNTV and halts count-up
Figure 9.12 Pulse Output Synchronized to TRGV Input
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9.4.7
Application Notes
The following types of contention can occur in timer V operation. Contention between TCNTV Write and Counter Clear: If a TCNTV clear signal is generated in the T3 state of a TCNTV write cycle, clearing takes precedence and the write to the counter is not carried out. Figure 9.13 shows the timing.
TCNTV write cycle by CPU T1 T2 T3
Address
TCNTV address
Internal write signal
Counter clear signal
TCNTV
N
H'00
Figure 9.13 Contention between TCNTV Write and Clear
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Contention between TCNTV Write and Increment: If a TCNTV increment clock signal is generated in the T3 state of a TCNTV write cycle, the write takes precedence and the counter is not incremented. Figure 9.14 shows the timing.
TCNTV write cycle by CPU T1 T2 T3
Address
TCNTV address
Internal write signal
TCNTV clock
TCNTV
N
M TCNTV write data
Figure 9.14 Contention between TCNTV Write and Increment
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Contention between TCOR Write and Compare Match: If a compare match is generated in the T3 state of a TCORA or TCORB write cycle, the write to TCORA or TCORB takes precedence and the compare match signal is inhibited. Figure 9.15 shows the timing.
TCORA write cycle by CPU T1 T2 T3
Address
TCORA address
Internal write signal
TCNTV
N
N+1
TCORA
N
M TCORA write data
Compare match signal Inhibited
Figure 9.15 Contention between TCORA Write and Compare Match
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Contention between Compare Match A and B: If compare match A and B occur simultaneously, any conflict between the output selections for compare match A and compare match B is resolved by following the priority order in table 9.12. Table 9.12 Timer Output Priority Order
Output Setting Toggle output 1 output 0 output No change Low Priority High
Internal Clock Switching and Counter Operation: Depending on the timing, TCNTV may be incremented by a switch between different internal clock sources. Table 9.13 shows the relation between internal clock switchover timing (by writing to bits CKS1 and CKS0) and TCNTV operation. When TCNTV is internally clocked, an increment pulse is generated from the falling edge of an internal clock signal, which is divided from the system clock (). For this reason, in a case like No. 3 in table 9.13 where the switch is from a high clock signal to a low clock signal, the switchover is seen as a falling edge, causing TCNTV to increment. TCNTV can also be incremented by a switch between internal and external clocks.
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Table 9.13 Internal Clock Switching and TCNTV Operation
Clock Levels Before and After Modifying Bits CKS1 and CKS0 Goes from low level 1 to low level*
No. 1
TCNTV Operation
Clock before switching Clock after switching Count clock
TCNTV
N Write to CKS1 and CKS0
N+1
2
Goes from low 2 to high*
Clock before switching Clock after switching Count clock
TCNTV
N
N+1
N+2
Write to CKS1 and CKS0
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Section 9 Timers Clock Levels Before and After Modifying Bits CKS1 and CKS0 Goes from high level 3 to low level*
No. 3
TCNTV Operation
Clock before switching
Clock after switching *4 Count clock
TCNTV
N
N+1 Write to CKS1 and CKS0
N+2
4
Goes from high to high
Clock before switching
Clock after switching Count clock
TCNTV
N
N+1
N+2 Write to CKS1 and CKS0
Notes: 1. Including a transition from the low level to the stopped state, or from the stopped state to the low level. 2. Including a transition from the stopped state to the high level. 3. Including a transition from the high level to the stopped state. 4. The switchover is seen as a falling edge, and TCNTV is incremented.
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9.5
9.5.1
Timer X
Overview
Timer X is based on a 16-bit free-running counter (FRC). It can output two independent waveforms, or measure input pulse widths and external clock periods. Features Features of timer X are given below. * Choice of three internal clock sources (/2, /8, /32) or an external clock (can be used as an external event counter). * Two independent output compare waveforms. * Four independent input capture channels, with selection of rising or falling edge and buffering option. * Counter can be cleared by compare match A. * Seven independent interrupt sources: two compare match, four input capture, one overflow
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Block Diagram Figure 9.16 shows a block diagram of timer X.
ICRA FTIA FTIB FTIC FTID Input capture control ICRC ICRB ICRD TCRX OCRB Comparator FRC FTCI Comparator FTOA FTOB OCRA TOCR
Internal data bus
PSS
TCSRX TIER Legend: TIER: TCSRX: FRC: OCRA: OCRB: TCRX: TOCR: ICRA: ICRB: ICRC: ICRD: PSS: Interrupt request Timer interrupt enable register Timer control/status register X Free-running counter Output compare register A Output compare register B Timer control register X Timer output compare control register Input capture register A Input capture register B Input capture register C Input capture register D Prescaler S
Figure 9.16 Block Diagram of Timer X
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Pin Configuration Table 9.14 shows the timer X pin configuration. Table 9.14 Pin Configuration
Name Counter clock input Output compare A Output compare B Input capture A Input capture B Input capture C Input capture D Abbr. FTCI FTOA FTOB FTIA FTIB FTIC FTID I/O Input Output Output Input Input Input Input Function Clock input to FRC Output pin for output compare A Output pin for output compare B Input pin for input capture A Input pin for input capture B Input pin for input capture C Input pin for input capture D
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Register Configuration Table 9.15 shows the register configuration of timer X. Table 9.15 Timer X Registers
Name Timer interrupt enable register Timer control/status register X Free-running counter H Free-running counter L Output compare register AH Output compare register AL Output compare register BH Output compare register BL Timer control register X Timer output compare control register Input capture register AH Input capture register AL Input capture register BH Input capture register BL Input capture register CH Input capture register CL Input capture register DH Input capture register DL Abbr. TIER TCSRX FRCH FRCL OCRAH OCRAL OCRBH OCRBL TCRX TOCR ICRAH ICRAL ICRBH ICRBL ICRCH ICRCL ICRDH ICRDL R/W R/W R/(W) R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R *1 Initial Value H'01 H'00 H'00 H'00 H'FF H'FF H'FF H'FF H'00 H'E0 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 Address H'F770 H'F771 H'F772 H'F773 H'F774* 2 H'F775*
2
H'F774* 2 H'F775*
2
H'F776 H'F777 H'F778 H'F779 H'F77A H'F77B H'F77C H'F77D H'F77E H'F77F
Notes: 1. Bits 7 to 1 can only be written with 0 for flag clearing. Bit 0 is a read/write bit. 2. OCRA and OCRB share the same address. They are selected by the OCRS bit in TOCR.
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9.5.2
Register Descriptions
Free-Running Counter (FRC) Free-Running Counter H (FRCH) Free-Running Counter L (FRCL)
FRC Bit Initial value Read/Write
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
FRCH
FRCL
FRC is a 16-bit read/write up-counter, which is incremented by internal or external clock input. The clock source is selected by bits CKS1 and CKS0 in TCRX. FRC can be cleared by compare match A, depending on the setting of CCLRA in TCSRX. When FRC overflows from H'FFFF to H'0000, OVF is set to 1 in TCSRX. If OVIE = 1 in TIER, a CPU interrupt is requested. FRC can be written and read by the CPU. Since FRC has 16 bits, data is transferred between the CPU and FRC via a temporary register (TEMP). For details see section 9.5.3, CPU Interface. FRC is initialized to H'0000 upon reset and in standby mode, watch mode, subsleep mode, and subactive mode. Output Compare Registers A and B (OCRA, OCRB) Output Compare Registers AH and BH (OCRAH, OCRBH) Output Compare Registers AL and BL (OCRAL, OCRBL)
OCRA, OCRB Bit Initial value Read/Write
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
OCRAH, OCRBH
OCRAL, OCRBL
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There are two 16-bit read/write output compare registers, OCRA and OCRB, the contents of which are always compared with FRC. When the values match, OCFA or OCFB is set to 1 in TCSRX. If OCIAE = 1 or OCIBE = 1 in TIER, a CPU interrupt is requested. When a compare match with OCRA or OCRB occurs, if OEA = 1 or OEB = 1 in TOCR, the value selected by OLVLA or OLVLB in TOCR is output at the FTOA or FTOB pin. After a reset, the output from the FTOA or FTOB pin is 0 until the first compare match occurs. OCRA and OCRB can be written and read by the CPU. Since they are 16-bit registers, data is transferred between them and the CPU via a temporary register (TEMP). For details see section 9.5.3, CPU Interface. OCRA and OCRB are initialized to H'FFFF upon reset and in standby mode, watch mode, subsleep mode, and subactive mode. Input Capture Registers A to D (ICRA to ICRD) Input Capture Registers AH to DH (ICRAH to ICRDH) Input Capture Registers AL to DL (ICRAL to ICRDL)
ICRA, ICRB, ICRC, ICRD Bit Initial value Read/Write
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
ICRAH, ICRBH, ICRCH, ICRDH
ICRAL, ICRBL, ICRCL, ICRDL
There are four 16-bit read only input capture registers, ICRA to ICRD. When the falling edge of an input capture signal is input, the FRC value is transferred to the corresponding input capture register, and the corresponding input capture flag (ICFA to ICFD) is set to 1 in TCSRX. If the corresponding input capture interrupt enable bit (ICIAE to ICIDE) is 1 in TCRX, a CPU interrupt is requested. The valid edge of the input signal can be selected by bits IEDGA to IEDGD in TCRX. ICRC and ICRD can also be used as buffer registers for ICRA and ICRB. Buffering is enabled by bits BUFEA and BUFEB in TCRX. Figure 9.17 shows the interconnections when ICRC operates as a buffer register of ICRA (when BUFEA = 1). When ICRC is used as the ICRA buffer, both the rising and falling edges of the
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external input signal can be selected simultaneously, by setting IEDGA IEDGC. If IEDGA = IEDGC, then only one edge is selected (either the rising edge or falling edge). See table 9.16. Note: The FRC value is transferred to the input capture register (ICR) regardless of the value of the input capture flag (ICF).
IEOGA BUFEA IEDGC
FTIA
Edge detector and internal capture signal generator
ICRC
ICRA
FRC
Figure 9.17 Buffer Operation (Example) Table 9.16 Input Edge Selection during Buffer Operation
IEDGA 0 1 IEDGC 0 1 0 1 Rising edge of input capture A input signal is captured Input Edge Selection Falling edge of input capture A input signal is captured (initial value) Rising and falling edge of input capture A input signal are both captured
ICRA to ICRD can be written and read by the CPU. Since they are 16-bit registers, data is transferred from them to the CPU via a temporary register (TEMP). For details see section 9.5.3, CPU Interface. To assure input capture, the pulse width of the input capture input signal must be at least 1.5 system clocks () when a single edge is selected, or at least 2.5 system clocks () when both edges are selected. ICRA to ICRD are initialized to H'0000 upon reset and in standby mode, watch mode, subsleep mode, and subactive mode.
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Timer Interrupt Enable Register (TIER)
Bit Initial value Read/Write 7 ICIAE 0 R/W 6 ICIBE 0 R/W 5 ICICE 0 R/W 4 ICIDE 0 R/W 3 OCIAE 0 R/W 2 OCIBE 0 R/W 1 OVIE 0 R/W 0 1
TIER is an 8-bit read/write register that enables or disables interrupt requests. TIER is initialized to H'01 upon reset and in standby mode, watch mode, subsleep mode, and subactive mode. Bit 7Input Capture Interrupt A Enable (ICIAE): Bit 7 enables or disables the ICIA interrupt requested when ICFA is set to 1 in TCSRX.
Bit 7: ICIAE 0 1 Description Interrupt request by ICFA (ICIA) is disabled Interrupt request by ICFA (ICIA) is enabled (initial value)
Bit 6Input Capture Interrupt B Enable (ICIBE): Bit 6 enables or disables the ICIB interrupt requested when ICFB is set to 1 in TCSRX.
Bit 6: ICIBE 0 1 Description Interrupt request by ICFB (ICIB) is disabled Interrupt request by ICFB (ICIB) is enabled (initial value)
Bit 5Input Capture Interrupt C Enable (ICICE): Bit 5 enables or disables the ICIC interrupt requested when ICFC is set to 1 in TCSRX.
Bit 5: ICICE 0 1 Description Interrupt request by ICFC (ICIC) is disabled Interrupt request by ICFC (ICIC) is enabled (initial value)
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Bit 4Input Capture Interrupt D Enable (ICIDE): Bit 4 enables or disables the ICID interrupt requested when ICFD is set to 1 in TCSRX.
Bit 4: ICIDE 0 1 Description Interrupt request by ICFD (ICID) is disabled Interrupt request by ICFD (ICID) is enabled (initial value)
Bit 3Output Compare Interrupt A Enable (OCIAE): Bit 3 enables or disables the OCIA interrupt requested when OCFA is set to 1 in TCSRX.
Bit 3: OCIAE 0 1 Description Interrupt request by OCFA (OCIA) is disabled Interrupt request by OCFA (OCIA) is enabled (initial value)
Bit 2Output Compare Interrupt B Enable (OCIBE): Bit 2 enables or disables the OCIB interrupt requested when OCFB is set to 1 in TCSRX.
Bit 2: OCIBE 0 1 Description Interrupt request by OCFB (OCIB) is disabled Interrupt request by OCFB (OCIB) is enabled (initial value)
Bit 1Timer Overflow Interrupt Enable (OVIE): Bit 1 enables or disables the FOVI interrupt requested when OVF is set to 1 in TCSRX.
Bit 1: OVIE 0 1 Description Interrupt request by OVF (FOVI) is disabled Interrupt request by OVF (FOVI) is enabled (initial value)
Bit 0Reserved Bit: Bit 0 is reserved; it is always read as 1, and cannot be modified.
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Timer Control/Status Register X (TCSRX)
Bit Initial value Read/Write Note: * 7 ICFA 0 R/(W)* 6 ICFB 0 R/(W)* 5 ICFC 0 R/(W)* 4 ICFD 0 R/(W)* 3 OCFA 0 R/(W)* 2 OCFB 0 R/(W)* 1 OVF 0 R/(W)* 0 CCLRA 0 R/W
Bits 7 to 1 can only be written with 0 for flag clearing.
TCSRX is an 8-bit register that selects clearing of the counter and controls interrupt request signals. TCSRX is initialized to H'00 upon reset and in standby mode, watch mode, subsleep mode, and subactive mode. Other timing is described in section 9.6.3, Timer Operation. Bit 7Input Capture Flag A (ICFA): Bit 7 is a status flag that indicates that the FRC value has been transferred to ICRA by an input capture signal. If BUFEA is set to 1 in TCRX, ICFA indicates that the FRC value has been transferred to ICRA by an input capture signal and that the ICRA value before this update has been transferred to ICRC. This flag is set by hardware and cleared by software. It cannot be set by software.
Bit 7: ICFA 0 1 Description Clearing condition: After reading ICFA = 1, cleared by writing 0 to ICFA (initial value)
Setting condition: Set when the FRC value is transferred to ICRA by an input capture signal
Bit 6Input Capture Flag B (ICFB): Bit 6 is a status flag that indicates that the FRC value has been transferred to ICRB by an input capture signal. If BUFEB is set to 1 in TCRX, ICFB indicates that the FRC value has been transferred to ICRB by an input capture signal and that the ICRB value before this update has been transferred to ICRC. This flag is set by hardware and cleared by software. It cannot be set by software.
Bit 6: ICFB 0 1 Description Clearing condition: After reading ICFB = 1, cleared by writing 0 to ICFB (initial value)
Setting condition: Set when the FRC value is transferred to ICRB by an input capture signal
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Bit 5Input Capture Flag C (ICFC): Bit 5 is a status flag that indicates that the FRC value has been transferred to ICRC by an input capture signal. If BUFEA is set to 1 in TCRX, ICFC is set by the input capture signal even though the FRC value is not transferred to ICRC. In buffered operation, ICFC can accordingly be used as an external interrupt, by setting the ICICE bit to 1. This flag is set by hardware and cleared by software. It cannot be set by software.
Bit 5: ICFC 0 1 Description Clearing condition: After reading ICFC = 1, cleared by writing 0 to ICFC Setting condition: Set by input capture signal (initial value)
Bit 4Input Capture Flag D (ICFD): Bit 4 is a status flag that indicates that the FRC value has been transferred to ICRD by an input capture signal. If BUFEB is set to 1 in TCRX, ICFD is set by the input capture signal even though the FRC value is not transferred to ICRD. In buffered operation, ICFD can accordingly be used as an external interrupt, by setting the ICIDE bit to 1. This flag is set by hardware and cleared by software. It cannot be set by software.
Bit 4: ICFD 0 1 Description Clearing condition: After reading ICFD = 1, cleared by writing 0 to ICFD Setting condition: Set by input capture signal (initial value)
Bit 3Output Compare Flag A (OCFA): Bit 3 is a status flag that indicates that the FRC value has matched OCRA. This flag is set by hardware and cleared by software. It cannot be set by software.
Bit 3: OCFA 0 1 Description Clearing condition: After reading OCFA = 1, cleared by writing 0 to OCFA Setting condition: Set when FRC matches OCRA (initial value)
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Bit 2Output Compare Flag B (OCFB): Bit 2 is a status flag that indicates that the FRC value has matched OCRB. This flag is set by hardware and cleared by software. It cannot be set by software.
Bit 2: OCFB 0 1 Description Clearing condition: After reading OCFB = 1, cleared by writing 0 to OCFB Setting condition: Set when FRC matches OCRB (initial value)
Bit 1Timer Overflow Flag (OVF): Bit 1 is a status flag that indicates that FRC has overflowed from H'FFFF to H'0000. This flag is set by hardware and cleared by software. It cannot be set by software.
Bit 1: OVF 0 1 Description Clearing condition: After reading OVF = 1, cleared by writing 0 to OVF Setting condition: Set when the FRC value overflows from H'FFFF to H'0000 (initial value)
Bit 0Counter Clear A (CCLRA): Bit 0 selects whether or not to clear FRC by compare match A (when FRC matches OCRA).
Bit 0: CCLRA 0 1 Description FRC is not cleared by compare match A FRC is cleared by compare match A (initial value)
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Timer Control Register X (TCRX)
Bit Initial value Read/Write 7 IEDGA 0 R/W 6 IEDGB 0 R/W 5 IEDGC 0 R/W 4 IEDGD 0 R/W 3 BUFEA 0 R/W 2 BUFEB 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W
TCRX is an 8-bit read/write register that selects the valid edges of the input capture signals, enables buffering, and selects the FRC clock source. TCRX is initialized to H'00 upon reset and in standby mode, watch mode, subsleep mode, and subactive mode. Bit 7Input Edge Select A (IEDGA): Bit 7 selects the rising or falling edge of the input capture A input signal (FTIA).
Bit 7: IEDGA 0 1 Description Falling edge of input capture A is captured Rising edge of input capture A is captured (initial value)
Bit 6Input Edge Select B (IEDGB): Bit 6 selects the rising or falling edge of the input capture B input signal (FTIB).
Bit 6: IEDGB 0 1 Description Falling edge of input capture B is captured Rising edge of input capture B is captured (initial value)
Bit 5Input Edge Select C (IEDGC): Bit 5 selects the rising or falling edge of the input capture C input signal (FTIC).
Bit 5: IEDGC 0 1 Description Falling edge of input capture C is captured Rising edge of input capture C is captured (initial value)
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Bit 4 Input Edge Select D (IEDGD): Bit 4 selects the rising or falling edge of the input capture D input signal (FTID).
Bit 4: IEDGD 0 1 Description Falling edge of input capture D is captured Rising edge of input capture D is captured (initial value)
Bit 3Buffer Enable A (BUFEA): Bit 3 selects whether or not to use ICRC as a buffer register for ICRA.
Bit 3: BUFEA 0 1 Description ICRC is not used as a buffer register for ICRA ICRC is used as a buffer register for ICRA (initial value)
Bit 2Buffer Enable B (BUFEB): Bit 2 selects whether or not to use ICRD as a buffer register for ICRB.
Bit 2: BUFEB 0 1 Description ICRD is not used as a buffer register for ICRB ICRD is used as a buffer register for ICRB (initial value)
Bits 1 and 0Clock Select (CKS1, CKS0): Bits 1 and 0 select one of three internal clock sources or an external clock for input to FRC. The external clock is counted on the rising edge.
Bit 1: CKS1 0 1 Bit 0: CKS0 0 1 0 1 Description Internal clock: /2 Internal clock: /8 Internal clock: /32 External clock: rising edge (initial value)
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Timer Output Compare Control Register (TOCR)
Bit Initial value Read/Write 7 1 6 1 5 1 4 OCRS 0 R/W 3 OEA 0 R/W 2 OEB 0 R/W 1 OLVLA 0 R/W 0 OLVLB 0 R/W
TOCR is an 8-bit read/write register that selects the output compare output levels, enables output compare output, and controls access to OCRA and OCRB. TOCR is initialized to H'E0 upon reset and in standby mode, watch mode, subsleep mode, and subactive mode. Bits 7 to 5Reserved Bits: Bit 7 to 5 are reserved; they are always read as 1, and cannot be modified. Bit 4Output Compare Register Select (OCRS): OCRA and OCRB share the same address. OCRS selects which register is accessed when this address is written or read. It does not affect the operation of OCRA and OCRB.
Bit 4: OCRS 0 1 Description OCRA is selected OCRB is selected (initial value)
Bit 3Output Enable A (OEA): Bit 3 enables or disables the timer output controlled by output compare A.
Bit 3: OEA 0 1 Description Output compare A output is disabled Output compare A output is enabled (initial value)
Bit 2Output Enable B (OEB): Bit 2 enables or disables the timer output controlled by output compare B.
Bit 2: OEB 0 1 Description Output compare B output is disabled Output compare B output is enabled (initial value)
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Bit 1Output Level A (OLVLA): Bit 1 selects the output level that is output at pin FTOA by compare match A (when FRC matches OCRA).
Bit 1: OLVLA 0 1 Description Low level High level (initial value)
Bit 0Output Level B (OLVLB): Bit 0 selects the output level that is output at pin FTOB by compare match B (when FRC matches OCRB).
Bit 0: OLVLB 0 1 Description Low level High level (initial value)
9.5.3
CPU Interface
FRC, OCRA, OCRB, and ICRA to ICRD are 16-bit registers, but the CPU is connected to the onchip peripheral modules by an 8-bit data bus. When the CPU accesses these registers, it therefore uses an 8-bit temporary register (TEMP). These registers should always be accessed 16 bits at a time. If two consecutive byte-size MOV instructions are used, the upper byte must be accessed first and the lower byte second. Data will not be transferred correctly if only the upper byte or only the lower byte is accessed.
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Write Access: Write access to the upper byte results in transfer of the upper-byte write data to TEMP. Next, write access to the lower byte results in transfer of the data in TEMP to the upper register byte, and direct transfer of the lower-byte write data to the lower register byte. Figure 9.18 shows an example of the writing of H'AA55 to FRC.
Write to upper byte
CPU (H'AA)
Bus interface
Module data bus
TEMP (H'AA)
FRCH ( )
FRCL ( )
Write to lower byte Module data bus
CPU (H'55)
Bus interface
TEMP (H'AA)
FRCH (H'AA)
FRCL (H'55)
Figure 9.18 Write Access to FRC (CPU FRC)
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Read Access: In access to FRC and ICRA to ICRD, when the upper byte is read the upper-byte data is transferred directly to the CPU and the lower-byte data is transferred to TEMP. Next, when the lower byte is read, the lower-byte data in TEMP is transferred to the CPU. In access to OCRA or OCRB, when the upper byte is read the upper-byte data is transferred directly to the CPU, and when the lower byte is read the lower-byte data is transferred directly to the CPU. Figure 9.19 shows an example of the reading of FRC when FRC contains H'AAFF.
Read upper byte
CPU (H'AA)
Bus interface
Module data bus
TEMP (H'FF)
FRCH (H'AA)
FRCL (H'FF)
Read lower byte Module data bus
CPU (H'FF)
Bus interface
TEMP (H'FF)
FRCH ( AB )
FRCL ( 00 )
Note: H'AB00 if counter has been updated once.
Figure 9.19 Read Access to FRC (FRC CPU)
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9.5.4
Timer Operation
Timer X Operation * Output compare operation Following a reset, FRC is initialized to H'0000 and starts counting up. Bits CKS1 and CKS0 in TCRX can select one of three internal clock sources or an external clock for input to FRC. The FRC contents are compared constantly with OCRA and OCRB. When a match occurs, the output at pin FTOA or FTOB goes to the level selected by OLVLA or OLVLB in TOCR. Following a reset, the output at both FTOA and FTOB is 0 until the first compare match. If CCLRA is set to 1 in TCSRX, compare match A clears FRC to H'0000. * Input capture operation Following a reset, FRC is initialized to H'0000 and starts counting up. Bits CKS1 and CKS0 in TCRX can select one of three internal clock sources or an external clock for input to FRC. When the edges selected by bits IEDGA to IEDGD in TCRX are input at pins FTIA to FTID, the FRC value is transferred to ICRA to ICRD, and ICFA to ICFD are set to 1 in TCSRX. If bits ICIAE to ICIDE are set to 1 in TIER, a CPU interrupt is requested. If bits BUFEA and BUFEB are set to 1 in TCRX, ICRC and ICRD operate as buffer registers for ICRA or ICRB. When the edges selected by bits IEDGA to IEDGD in TCRX are input at pins FTIA and FTIB, the FRC value is transferred to ICRA or ICRB, and the previous value in ICRA or ICRB is transferred to ICRC or ICRD. Simultaneously, ICFA or ICFB is set to 1. If bit ICIAE or ICIBE is set to 1 in TIER, a CPU interrupt is requested.
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FRC Count Timing: FRC is incremented by clock input. Bits CKS1 and CKS0 in TCRX can select one of three internal clock sources (/2, /8, /32) or an external clock. * Internal clock Bits CKS1 and CKS0 in TCRX select one of three internal clock sources (/2, /8, /32) created by dividing the system clock (). Figure 9.20 shows the increment timing.
Internal clock
FRC input clock
FRC
N-1
N
N+1
Figure 9.20 Increment Timing with Internal Clock * External clock External clock input is selected when bits CKS1 and CKS0 are both set to 1 in TCRX. FRC increments on the rising edge of the external clock. An external pulse width of at least 1.5 system clocks () is necessary. Shorter pulses will not be counted correctly. Figure 9.21 shows the timing.
FTCI (external clock input pin) FRC input clock
FRC
N
N-1
Figure 9.21 Increment Timing with External Clock
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Output Compare Timing: When a compare match occurs, the output level selected by the OLVL bit in TOCR is output at pin FTOA or FTOB. Figure 9.22 shows the output timing for output compare A.
FRC
N
N+1
N
N+1
OCRA
N
N
Compare match A signal Clear* OLVLA
FTOA (output compare A output pin) Note: * By execution of a software instruction.
Figure 9.22 Output Compare A Output Timing FRC Clear Timing: FRC can be cleared by compare match A. Figure 9.23 shows the timing.
Compare match A signal
FRC
N
H'0000
Figure 9.23 Clear Timing by Compare Match A
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Input Capture Timing * Input capture timing The rising or falling edge is selected for input capture by bits IEDGA to IEDGD in TCRX. Figure 9.24 shows the timing when the rising edge is selected (IEDGA/B/C/D = 1).
Input capture pin Input capture signal
Figure 9.24 Input Capture Signal Timing (Normal Case) If the input at the input capture pin occurs while the upper byte of the corresponding input capture register (ICRA to ICRD) is being read, the internal input capture signal is delayed by one system clock (). Figure 9.25 shows the timing.
ICRA to ICRD upper byte read cycle T1 T2 T3
Input capture pin
Input capture signal
Figure 9.25 Input Capture Signal Timing (during ICRA to ICRD Read)
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* Buffered input capture timing Input capture can be buffered by using ICRC or ICRD as a buffer for ICRA or ICRB. Figure 9.26 shows the timing when ICRA is buffered by ICRC (BUFEA = 1) and both the rising and falling edges are selected (IEDGA = 1 and IEDGC = 0, or IEDGA = 0 and IEDGC = 1).
FTIA
Input capture signal
FRC
n
n+1
N
N+1
ICRA
M
n
n
N
ICRC
m
M
M
n
Figure 9.26 Buffered Input Capture Timing (Normal Case) When ICRC or ICRD is used as a buffer register, the input capture flag is still set by the selected edge of the input capture input signal. For example, if ICRC is used to buffer ICRA, when the edge transition selected by the IEDGC bit occurs at the input capture pin, ICFC will be set, and if the ICIEC bit is set, an interrupt will be requested. The FRC value will not be transferred to ICRC, however. In buffered operation, if the upper byte of one of the two registers that receives a data transfer (ICRA and ICRC, or ICRB and ICRD) is being read when an input capture signal would normally occur, the input capture signal will be delayed by one system clock (). Figure 9.27 shows the case when BUFEA = 1.
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ICRA or ICRC upper byte read cycle by CPU T1 T2 T3
FTIA
Input capture signal
Figure 9.27 Buffered Input Capture Signal Timing (during ICRA or ICRD Read) Input Capture Flag (ICFA to ICFD) Set Timing: Figure 9.28 shows the timing when an input capture flag (ICFA to ICFD) is set to 1 and the FRC value is transferred to the corresponding input capture register (ICRA to ICRD).
Input capture signal
ICFA to ICFD
FRC
N
ICRA to ICRD
N
Figure 9.28 ICFA to ICFD Set Timing
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Output Compare Flag (OCFA or OCFB) Set Timing: OCFA and OCFB are set to 1 by internal compare match signals that are output when FRC matches OCRA or OCRB. The compare match signal is generated in the last state during which the values match (when FRC is updated from the matching value to a new value). When FRC matches OCRA or OCRB, the compare match signal is not generated until the next counter clock. Figure 9.29 shows the OCFA and OCFB set timing.
FRC
N
N+1
OCRA, OCRB
N
Compare match signal
OCFA, OCFB
Figure 9.29 OCFA and OCFB Set Timing Overflow Flag (OVF) Set Timing: OVF is set to 1 when FRC overflows from H'FFFF to H'0000. Figure 9.30 shows the timing.
FRC
H'FFFF
H'0000
Overflow signal
OVF
Figure 9.30 OVF Set Timing
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9.5.5
Timer X Operation Modes
Table 9.17 shows the timer X operation modes. Table 9.17 Timer X Operation Modes
Operation Mode FRC OCRA, OCRB ICRA to ICRD TIER TCRX TOCR TCSRX Reset Reset Reset Reset Reset Reset Reset Reset Active Functions Functions Functions Functions Functions Functions Functions Sleep Functions Functions Functions Functions Functions Functions Functions Watch Reset Reset Reset Reset Reset Reset Reset Subactive Reset Reset Reset Reset Reset Reset Reset Subsleep Reset Reset Reset Reset Reset Reset Reset Standby Reset Reset Reset Reset Reset Reset Reset
9.5.6
Interrupt Sources
Timer X has three types of interrupts and seven interrupt sources: ICIA to ICID, OCIA, OCIB, and FOVI. Table 9.18 lists the sources of interrupt requests. Each interrupt source can be enabled or disabled by an interrupt enable bit in TIER. Although all seven interrupts share the same vector, they have individual interrupt flags, so software can discriminate the interrupt source. Table 9.18 Timer X Interrupt Sources
Interrupt ICIA ICIB ICIC ICID OCIA OCIB FOVI Description Interrupt requested by ICFA Interrupt requested by ICFB Interrupt requested by ICFC Interrupt requested by ICFD Interrupt requested by OCFA Interrupt requested by OCFB Interrupt requested by OVF Vector Address H'0020
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9.5.7
Timer X Application Example
Figure 9.31 shows an example of the output of pulse signals with a 50% duty cycle and arbitrary phase offset. To set up this output: * Set bit CCLRA to 1 in TCSRX. * Have software invert the OLVLA and OLVLB bits at each corresponding compare match.
FRC H'FFFF OCRA OCRB H'0000 FTOA Counter cleared
FTOB
Figure 9.31 Pulse Output Example
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9.5.8
Application Notes
The following types of contention can occur in timer X operation. 1. Contention between FRC write and counter clear If an FRC clear signal is generated in the T3 state of a write cycle to the lower byte of FRC, clearing takes precedence and the write to the counter is not carried out. Figure 9.32 shows the timing.
FRC lower byte write cycle T1 T2 T3
Address
FRC address
Internal write signal
Counter clear signal
FRC
N
H'0000
Figure 9.32 Contention between FRC Write and Clear
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2. Contention between FRC write and increment If an FRC increment clock signal is generated in the T3 state of a write cycle to the lower byte of FRC, the write takes precedence and the counter is not incremented. Figure 9.33 shows the timing.
FRC lower byte write cycle T1 T2 T3
Address
FRC address
Internal write signal
FRC input clock
FRC
N
M FRC write data
Figure 9.33 Contention between FRC Write and Increment
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3. Contention between OCR write and compare match If a compare match is generated in the T3 state of a write cycle to the lower byte of OCRA or OCRB, the write to OCRA or OCRB takes precedence and the compare match signal is inhibited. Figure 9.34 shows the timing.
OCR lower byte write cycle T1 T2 T3
Address
OCR address
Internal write signal
FRC
N
N+1
OCR
N
M Write data
Compare match signal Inhibited
Figure 9.34 Contention between OCR Write and Compare Match
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4. Internal clock switching and counter operation Depending on the timing, FRC may be incremented by a switch between different internal clock sources. Table 9.19 shows the relation between internal clock switchover timing (by writing to bits CKS1 and CKS0) and FRC operation. When FRC is internally clocked, an increment pulse is generated from the falling edge of an internal clock signal, which is divided from the system clock (). For this reason, in a case like No. 3 in table 9.19 where the switch is from a high clock signal to a low clock signal, the switchover is seen as a falling edge, causing FRC to increment. FRC can also be incremented by a switch between internal and external clocks. Table 9.19 Internal Clock Switching and FRC Operation
Clock Levels Before and After Modifying Bits CKS1 and CKS0 Goes from low level to low level
No. 1
FRC Operation
Clock before switching Clock after switching Count clock
FRC
N Write to CKS1 and CKS0
N+1
2
Goes from low to high
Clock before switching Clock after switching Count clock
FRC
N
N+1
N+2
Write to CKS1 and CKS0
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Section 9 Timers Clock Levels Before and After Modifying Bits CKS1 and CKS0 Goes from high level to low level
No. 3
FRC Operation
Clock before switching
Clock after switching * Count clock
FRC
N
N+1 Write to CKS1 and CKS0
N+2
4
Goes from high to high
Clock before switching
Clock after switching Count clock
FRC
N
N+1
N+2 Write to CKS1 and CKS0
Note:
*
The switchover is seen as a falling edge, and FRC is incremented.
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9.6
9.6.1
Watchdog Timer
Overview
The watchdog timer has an 8-bit counter that is incremented by an input clock. If a system runaway allows the counter value to overflow before being rewritten, the watchdog timer can reset the chip internally. Features Features of the watchdog timer are given below. * Incremented by internal clock source (/8192). * A reset signal is generated when the counter overflows. The overflow period can be set from 1 to 256 times 8192/ (from approximately 2 ms to 500 ms when = 4.19 MHz). Block Diagram Figure 9.35 shows a block diagram of the watchdog timer.
TCSRW
PSS
/8192
TCW
Legend: TCSRW: Timer control/status register W TCW: Timer counter W PSS: Prescaler S
Internal reset signal
Figure 9.35 Block Diagram of Watchdog Timer
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Internal data bus
Section 9 Timers
Register Configuration Table 9.20 shows the register configuration of the watchdog timer. Table 9.20
Name Timer control/status register W Timer counter W
Watchdog Timer Registers
Abbr. TCSRW TCW R/W R/W R/W Initial Value H'AA H'00 Address H'FFBE H'FFBF
9.6.2
Register Descriptions
Timer Control/Status Register W (TCSRW)
Bit Initial value Read/Write Note: * 7 B6WI 1 R 6 TCWE 0 R/(W)* 5 B4WI 1 R 4 TCSRWE 0 R/(W)* 3 B2WI 1 R 2 WDON 0 R/(W)* 1 B0WI 1 R 0 WRST 0 R/(W)*
Write is permitted only under certain conditions, which are given in the descriptions of the individual bits.
TCSRW is an 8-bit read/write register that controls write access to TCW and TCSRW itself, controls watchdog timer operations, and indicates operating status. Bit 7Bit 6 Write Inhibit (B6WI): Bit 7 controls the writing of data to bit 6 in TCSRW. This bit is always read as 1. Data written to this bit is not stored.
Bit 7: B6WI 0 1 Description Bit 6 is write-enabled Bit 6 is write-protected (initial value)
Bit 6Timer Counter W Write Enable (TCWE): Bit 6 controls the writing of data to bit 8 to TCW.
Bit 6: TCWE 0 1 Description Data cannot be written to TCW Data can be written to TCW (initial value)
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Bit 5Bit 4 Write Inhibit (B4WI): Bit 5 controls the writing of data to bit 4 in TCSRW. This bit is always read as 1. Data written to this bit is not stored.
Bit 5: B4WI 0 1 Description Bit 4 is write-enabled Bit 4 is write-protected (initial value)
Bit 4Timer Control/Status Register W Write Enable (TCSRWE): Bit 4 controls the writing of data to TCSRW bits 2 and 0.
Bit 4: TCSRWE 0 1 Description Data cannot be written to bits 2 and 0 Data can be written to bits 2 and 0 (initial value)
Bit 3Bit 2 Write Inhibit (B2WI): Bit 3 controls the writing of data to bit 2 in TCSRW. This bit is always read as 1. Data written to this bit is not stored.
Bit 3: B2WI 0 1 Description Bit 2 is write-enabled Bit 2 is write-protected (initial value)
Bit 2Watchdog Timer On (WDON): Bit 2 enables watchdog timer operation. Counting starts when this bit is set to 1, and stops when this bit is cleared to 0.
Bit 2: WDON 0 Description Watchdog timer operation is disabled (initial value) Clearing condition: Reset, or when TCSRWE = 1 and 0 is written in both B2WI and WDON 1 Watchdog timer operation is enabled Setting condition: When TCSRWE = 1 and 0 is written in B2WI and 1 is written in WDON
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Bit 1Bit 0 Write Inhibit (B0WI): Bit 1 controls the writing of data to bit 0 in TCSRW. This bit is always read as 1. Data written to this bit is not stored.
Bit 1: B0WI 0 1 Description Bit 0 is write-enabled Bit 0 is write-protected (initial value)
Bit 0Watchdog Timer Reset (WRST): Bit 0 indicates that TCW has overflowed, generating an internal reset signal. The internal reset signal generated by the overflow resets the entire chip. WRST is cleared to 0 by a reset from the RES pin, or when software writes 0.
Bit 0: WRST 0 Description Clearing conditions: * Reset by RES pin * 1 When TCSRWE = 1, and 0 is written in both B0WI and WRST Setting condition: When TCW overflows and an internal reset signal is generated (initial value)
Timer Counter W (TCW)
Bit Initial value Read/Write 7 TCW7 0 R/W 6 TCW6 0 R/W 5 TCW5 0 R/W 4 TCW4 0 R/W 3 TCW3 0 R/W 2 TCW2 0 R/W 1 TCW1 0 R/W 0 TCW0 0 R/W
TCW is an 8-bit read/write up-counter, which is incremented by internal clock input. The input clock is /8192. The TCW value can always be written or read by the CPU. When TCW overflows from H'FF to H'00, an internal reset signal is generated and WRST is set to 1 in TCSRW. Upon reset, TCW is initialized to H'00.
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9.6.3
Timer Operation
The watchdog timer has an 8-bit counter (TCW) that is incremented by clock input (/8192). When TCSRWE = 1 in TCSRW, if 0 is written in B2WI and 1 is simultaneously written in WDON, TCW starts counting up (two write accesses to TCSRW are necessary in order to operate the watchdog timer). When the TCW count value reaches H'FF, the next clock input causes the watchdog timer to overflow and generates an internal reset signal. The internal reset signal is output for 512 clock cycles of the OSC clock. It is possible to write to TCW, causing TCW to count up from the written value. The overflow period can be set in the range from 1 to 256 input clocks, depending on the value written in TCW. Figure 9.36 shows an example of watchdog timer operations. Example: = 4 MHz and the desired overflow period is 30 ms.
4 x 106 x 30 x 10-3 = 14.6 8192
The value set in TCW should therefore be 256 - 15 = 241 (H'F1).
TCW overflow
H'FF H'F1 TCW count value
H'00 Start H'F1 written in TCW Internal reset signal 512 OSC clock cycles H'F1 written in TCW Reset
Figure 9.36 Typical Watchdog Timer Operations (Example)
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Section 9 Timers
9.6.4
Watchdog Timer Operation States
Table 9.21 summarizes the watchdog timer operation states. Table 9.21 Watchdog Timer Operation States
Operation Mode TCW TCSRW Reset Reset Reset Active Functions Functions Sleep Functions Functions Watch Halted Retained Subactive Halted Subsleep Halted Standby Halted
Retained Retained Retained
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Section 10 Serial Communication Interface
Section 10 Serial Communication Interface
10.1 Overview
The H8/3644 Group is provided with a two-channel serial communication interface (SCI). Table 10.1 summarizes the functions and features of the two SCI channels. Table 10.1 Serial Communication Interface Functions
Channel SCI1 Functions Synchronous serial transfer * * Choice of 8-bit or 16-bit data length Continuous clock output * * SCI3 Synchronous serial transfer * * 8-bit data length Send, receive, or simultaneous send/receive Multiprocessor communication Choice of 7-bit or 8-bit data length Choice of 1 or 2 stop bits Parity addition * * * * Features * Choice of 8 internal clocks (/1024 to /2) or external clock Open drain output possible Interrupt requested at completion of transfer On-chip baud rate generator Receive error detection Break detection Interrupt requested at completion of transfer or error
Asynchronous serial transfer * * * *
10.2
10.2.1
SCI1
Overview
Serial communication interface 1 (SCI1) performs synchronous serial transfer of 8-bit or 16-bit data. SSB (Synchronized Serial Bus) communication is also provided, enabling multiple ICs to be controlled.
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Section 10 Serial Communication Interface
Features * Choice of 8-bit or 16-bit data length * Choice of eight internal clock sources (/1024, /256, /64, /32, /16, /8, /4, /2) or an external clock * Interrupt requested at completion of transfer * Choice of HOLD mode or LATCH mode in SSB mode. Block Diagram Figure 10.1 shows a block diagram of SCI1.
PSS
SCK1
SCR1
Transfer bit counter
SI1
SDRU
SDRL SO1 IRRS1 Legend: SCR1: SCSR1: SDRU: SDRL: IRRS1: PSS: Serial control register 1 Serial control/status register 1 Serial data register U Serial data register L SCI1 interrupt request flag Prescaler S
Figure 10.1 SCI1 Block Diagram
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Internal data bus
Transmit/receive control circuit
SCSR1
Section 10 Serial Communication Interface
Pin Configuration Table 10.2 shows the SCI1 pin configuration. Table 10.2 Pin Configuration
Name SCI1 clock pin SCI1 data input pin SCI1 data output pin Abbr. SCK1 SI1 SO1 I/O I/O Input Output Function SCI1 clock input or output SCI1 receive data input SCI1 transmit data output
Register Configuration Table 10.3 shows the SCI1 register configuration. Table 10.3 SCI1 Registers
Name Serial control register 1 Serial control status register 1 Serial data register U Serial data register L Abbr. SCR1 SCSR1 SDRU SDRL R/W R/W R/W R/W R/W Initial Value H'00 H'9C Undefined Undefined Address H'FFA0 H'FFA1 H'FFA2 H'FFA3
10.2.2
Register Descriptions
Serial Control Register 1 (SCR1)
Bit Initial value Read/Write 7 SNC1 0 R/W 6 SNC0 0 R/W 5 MRKON 0 R/W 4 LTCH 0 R/W 3 CKS3 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W
SCR1 is an 8-bit read/write register for selecting the operation mode, the transfer clock source, and the prescaler division ratio. Upon reset, SCR1 is initialized to H'00. Writing to this register during a transfer stops the transfer.
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Bits 7 and 6Operation Mode Select 1, 0 (SNC1, SNC0): Bits 7 and 6 select the operation mode.
Bit 7: SNC1 0 1 Bit 6: SNC0 0 1 0 1 Description 8-bit synchronous transfer mode 16-bit synchronous transfer mode 1 Continuous clock output mode* Reserved*
2
(initial value)
Notes: 1. Pins SI1 and SO1 should be used as general input or output ports. 2. Don't set bits SNC1 and SNC0 to 11.
Bits 5TAIL MARK Control (MRKON): Bit 5 controls TAIL MARK output after an 8- or 16 bit data transfer.
Bit 5: MRKON 0 1 Description TAIL MARK is not output (synchronous mode) TAIL MARK is output (SSB mode) (initial value)
Bits 4LATCH TAIL Select (LTCH): Bit 4 selects whether LATCH TAIL or HOLD TAIL is output as TAIL MARK when bit MRKON is set to 1 (SSB mode).
Bit 4: LTCH 0 1 Description HOLD TAIL is output LATCH TAIL is output (initial value)
Bit 3Clock Source Select (CKS3): Bit 3 selects the clock source and sets pin SCK1 as an input or output pin.
Bit 3: CKS3 0 1 Description Clock source is prescaler S, and pin SCK1 is output pin Clock source is external clock, and pin SCK1 is input pin (initial value)
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Section 10 Serial Communication Interface
Bits 2 to 0Clock Select (CKS2 to CKS 0): When CKS3 = 0, bits 2 to 0 select the prescaler division ratio and the serial clock cycle.
Serial Clock Cycle Bit 2: CKS2 0 Bit 1: CKS1 0 1 1 0 1 Bit 0: CKS0 0 1 0 1 0 1 0 1 Prescaler Division /1024 (initial value) /256 /64 /32 /16 /8 /4 /2 = 5 MHz 204.8 s 51.2 s 12.8 s 6.4 s 3.2 s 1.6 s 0.8 s = 2.5 MHz 409.6 s 102.4 s 25.6 s 12.8 s 6.4 s 3.2 s 1.6 s 0.8 s
Serial Control/Status Register 1 (SCSR1)
Bit Initial value Read/Write Note: * 7 1 6 SOL 0 R/W 5 ORER 0 R/(W)* 4 1 3 1 2 1 1 MTRF 0 R 0 STF 0 R/W
Only a write of 0 for flag clearing is possible.
SCSR1 is an 8-bit register indicating operation status and error status. Upon reset, SCSR1 is initialized to H'9C. Bit 7Reserved Bit: Bit 7 is reserved; it is always read as 1, and cannot be modified.
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Bit 6Extended Data Bit (SOL): Bit 6 sets the SO1 output level. When read, SOL returns the output level at the SO1 pin. After completion of a transmission, SO1 continues to output the value of the last bit of transmitted data. The SO1 output can be changed by writing to SOL before or after a transmission. The SOL bit setting remains valid only until the start of the next transmission. SSB mode settings also become invalid. To control the level of the SO1 pin after transmission ends, it is necessary to write to the SOL bit at the end of each transmission. Do not write to this register while transmission is in progress, because that may cause a malfunction.
Bit 6: SOL 0 1 Description Read: SO1 pin output level is low Write: SO1 pin output level changes to low Read: SO1 pin output level is high Write: SO1 pin output level changes to high (initial value)
Bit 5Overrun Error Flag (ORER): When an external clock is used, bit 5 indicates the occurrence of an overrun error. If noise occurs during a transfer, causing an extraneous pulse to be superimposed on the normal serial clock, incorrect data may be transferred. If a clock pulse is input after transfer completion, this bit is set to 1 indicating an overrun.
Bit 5: ORER 0 1 Description Clearing condition: After reading ORER = 1, cleared by writing 0 to ORER (initial value)
Setting condition: Set if a clock pulse is input after transfer is complete, when an external clock is used
Bits 4 to 2Reserved Bits: Bits 4 to 2 are reserved. They are always read as 0, and cannot be modified. Bit 1TAIL MARK Transmit Flag (MTRF): When bit MRKON is set to 1, bit 1 indicates that TAIL MARK is being sent. Bit 1 is a read-only bit and cannot be modified.
Bit 1: MTRF 0 1 Description Idle state, or 8- or 16-bit data is being transferred TAIL MARK is being sent (initial value)
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Section 10 Serial Communication Interface
Bit 0Start Flag (STF): Bit 0 controls the start of a transfer. Setting this bit to 1 causes SCI1 to start transferring data. During the transfer or while waiting for the first clock pulse, this bit remains set to 1. It is cleared to 0 upon completion of the transfer. It can therefore be used as a busy flag.
Bit 0: STF 0 1 Description Read: Indicates that transfer is stopped Write: Invalid Read: Indicates transfer in progress Write: Starts a transfer operation (initial value)
Serial Data Register U (SDRU)
Bit Initial value Read/Write 7 SDRU7 R/W 6 SDRU6 R/W 5 SDRU5 R/W 4 SDRU4 R/W 3 SDRU3 R/W 2 SDRU2 R/W 1 SDRU1 R/W 0 SDRU0 R/W
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
SDRU is an 8-bit read/write register. It is used as the data register for the upper 8 bits in 16-bit transfer (SDRL is used for the lower 8 bits). Data written to SDRU is output to SDRL starting from the least significant bit (LSB). This data is then replaced by LSB-first data input at pin SI1, which is shifted in the direction from the most significant bit (MSB) toward the LSB. SDRU must be written or read only after data transmission or reception is complete. If this register is written or read while a data transfer is in progress, the data contents are not guaranteed. The SDRU value upon reset is undefined. Serial Data Register L (SDRL)
Bit Initial value Read/Write 7 SDRL7 R/W 6 SDRL6 R/W 5 SDRL5 R/W 4 SDRL4 R/W 3 SDRL3 R/W 2 SDRL2 R/W 1 SDRL1 R/W 0 SDRL0 R/W
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
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Section 10 Serial Communication Interface
SDRL is an 8-bit read/write register. It is used as the data register in 8-bit transfer, and as the data register for the lower 8 bits in 16-bit transfer (SDRU is used for the upper 8 bits). In 8-bit transfer, data written to SDRL is output from pin SO1 starting from the least significant bit (LSB). This data is then replaced by LSB-first data input at pin SI1, which is shifted in the direction from the most significant bit (MSB) toward the LSB. In 16-bit transfer, operation is the same as for 8-bit transfer, except that input data is fed in via SDRU. SDRL must be written or read only after data transmission or reception is complete. If this register is read or written while a data transfer is in progress, the data contents are not guaranteed. The SDRL value upon reset is undefined. 10.2.3 Operation in Synchronous Mode
Data can be sent and received in an 8-bit or 16-bit format, with an internal or external clock selected as the clock source. Overrun errors can be detected when an external clock is used. Clock: The serial clock can be selected from a choice of eight internal clocks and an external clock. When an internal clock source is selected, pin SCK1 becomes the clock output pin. When continuous clock output mode is selected (SCR1 bits SNC1 and SNC0 are set to 10), the clock signal (/1024 to /2) selected in bits CKS2 to CKS0 is output continuously from pin SCK1. When an external clock is used, pin SCK1 is the clock input pin. Data Transfer Format: Figure 10.2 shows the data transfer format. Data is sent and received starting from the least significant bit, in LSB-first format. Transmit data is output from one falling edge of the serial clock until the next rising edge. Receive data is latched at the rising edge of the serial clock.
SCK 1 SO1 /SI 1 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
Figure 10.2 Transfer Format
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Section 10 Serial Communication Interface
Data Transfer Operations Transmitting: A transmit operation is carried out as follows. 1. Set bits SO1 and SCK1 to 1 in PMR3 to select the SO1 and SCK1 pin functions. If necessary, set bit POF1 in PMR7 for NMOS open-drain output at pin SO1. 2. Clear bit SNC1 in SCR1 to 0, set bit SNC0 to 0 or 1, and clear bit MRKON to 0, designating 8- or 16-bit synchronous transfer mode. Select the serial clock in bits CKS3 to CKS0. Writing data to SCR1 when bit MRKON in SCR1 is cleared to 0 initializes the internal state of SCI1. 3. Write transmit data in SDRL and SDRU, as follows. 8-bit transfer mode: SDRL 16-bit transfer mode: Upper byte in SDRU, lower byte in SDRL 4. Set the SCSR1 start flag (STF) to 1. SCI1 starts operating and outputs transmit data at pin SO1. 5. After data transmission is complete, bit IRRS1 in interrupt request register 2 (IRR2) is set to 1.
When an internal clock is used, a serial clock is output from pin SCK1 in synchronization with the transmit data. After data transmission is complete, the serial clock is not output until the next time the start flag is set to 1. During this time, pin SO1 continues to output the value of the last bit transmitted. When an external clock is used, data is transmitted in synchronization with the serial clock input at pin SCK1. After data transmission is complete, an overrun occurs if the serial clock continues to be input; no data is transmitted and the SCSR1 overrun error flag (bit ORER) is set to 1. While transmission is stopped, the output value of pin SO1 can be changed by rewriting bit SOL in SCSR1. Receiving: A receive operation is carried out as follows. 1. Set bits SI1 and SCK1 to 1 in PMR3 to select the SI1 and SCK1 pin functions. 2. Clear bit SNC1 in SCR1 to 0, set bit SNC0 to 0 or 1, and clear bit MRKON to 0, designating 8- or 16-bit synchronous transfer mode. Select the serial clock in bits CKS3 to CKS0. Writing data to SCR1 when bit MRKON in SCR1 is cleared to 0 initializes the internal state of SCI1. 3. Set the SCSR1 start flag (STF) to 1. SCI1 starts operating and receives data at pin SI1. 4. After data reception is complete, bit IRRS1 in interrupt request register 2 (IRR2) is set to 1. 5. Read the received data from SDRL and SDRU, as follows. 8-bit transfer mode: SDRL 16-bit transfer mode: Upper byte in SDRU, lower byte in SDRL
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Section 10 Serial Communication Interface
6.
After data reception is complete, an overrun occurs if the serial clock continues to be input; no data is received and the SCSR1 overrun error flag (bit ORER) is set to 1.
Simultaneous Transmit/Receive: A simultaneous transmit/receive operation is carried out as follows. 1. Set bits SO1, SI1, and SCK1 to 1 in PMR3 to select the SO1, SI1, and SCK1 pin functions. If necessary, set bit POF1 in PMR7 for NMOS open-drain output at pin SO1. 2. Clear bit SNC1 in SCR1 to 0, set bit SNC0 to 0 or 1, and clear bit MRKON to 0, designating 8- or 16-bit synchronous transfer mode. Select the serial clock in bits CKS3 to CKS0. Writing data to SCR1 when bit MRKON in SCR1 is cleared to 0 initializes the internal state of SCI1. 3. Write transmit data in SDRL and SDRU, as follows. 8-bit transfer mode: SDRL 16-bit transfer mode: Upper byte in SDRU, lower byte in SDRL 4. Set the SCSR1 start flag (STF) to 1. SCI1 starts operating. Transmit data is output at pin SO1. Receive data is input at pin SI1. 5. After data transmission and reception are complete, bit IRRS1 in IRR2 is set to 1. 6. Read the received data from SDRL and SDRU, as follows. 8-bit transfer mode: SDRL 16-bit transfer mode: Upper byte in SDRU, lower byte in SDRL When an internal clock is used, a serial clock is output from pin SCK1 in synchronization with the transmit data. After data transmission is complete, the serial clock is not output until the next time the start flag is set to 1. During this time, pin SO1 continues to output the value of the last bit transmitted. When an external clock is used, data is transmitted and received in synchronization with the serial clock input at pin SCK1. After data transmission and reception are complete, an overrun occurs if the serial clock continues to be input; no data is transmitted or received and the SCSR1 overrun error flag (bit ORER) is set to 1. While transmission is stopped, the output value of pin SO1 can be changed by rewriting bit SOL in SCSR1.
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Section 10 Serial Communication Interface
10.2.4
Operation in SSB Mode
SSB communication uses two lines, SCL (Serial Clock) and SDA (Serial Data), and enables multiple ICs to be connected as shown in figure 10.3. In SSB mode, TAIL MARK is sent after an 8- or 16-bit data transfer. HOLD TAIL or LATCH TAIL can be selected as TAIL MARK.
H8/3644 SCK 1 Group SO1
SCL SDA
SDA
SDA
IC-A
IC-B
IC-C
Figure 10.3 Example of SSB Connection Clock: The transfer clock can be selected from eight internal clocks or an external clock, but since the H8/3644 Group uses clock output, an external clock should not be selected. The transfer rate can be selected by bits CKS2 to CKS0 in SCR1. Since this is also the TAIL MARK transfer rate, the setting should be made to give a transfer clock cycle of at least 2 s. Data Transfer Format: Figure 10.4 shows the SCI1 transfer format. Data is sent starting from the least significant bit, in LSB-first format. TAIL MARK is sent after an 8- or 16-bit data transfer.
SCK1
SO 1
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5 Bit 14 Bit 15 TAIL MARK 1 frame
Figure 10.4 Transfer Format (When SNC1 = 0, SNC0 = 1, MRKON = 1)
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SDA
SCL
SCL
SCL
Section 10 Serial Communication Interface
TAIL MARK: TAIL MARK can be either HOLD TAIL or LATCH TAIL. The output waveforms of HOLD TAIL and LATCH TAIL are shown in figure 10.5. Time t in the figure is determined by the transfer clock cycle set in bits CKS2 to CKS0 in SCR1.
< HOLD TAIL > SCK1 t SO 1 t t 2t t t t SO 1 SCK1 t t t 2t t t < LATCH TAIL >
Bit 14 Bit 15
Bit 0
Bit 14 Bit 15
Figure 10.5 HOLD TAIL and LATCH TAIL Waveforms Transmitting: A transmit operation is carried out as follows. 1. Set bit SOL in SCSR1 to 1. 2. Set bits SO1 and SCK1 to 1 in PMR3 to select the S01 and SCK1 pin functions. Set bit POF1 in PMR7 to 1 for NMOS open-drain output at pin SO1. 3. Clear bit SNC1 in SCR1 to 0 and set bit SNC0 to 0 or 1, designating 8-bit mode or 16-bit mode. Set bit MRKON in SCR1 to 1, selecting SSB mode. 4. Write transmit data in SDRL and SDRU as follows, and select TAIL MARK with bit LTCH in SCR1. 8-bit mode: SDRL 16-bit mode: Upper byte in SDRU, lower byte in SDRL 5. Set the SCSR1 start flag (STF) to 1. SCI1 starts operating and outputs transmit data at pin S01. 6. After 8- or 16-bit data transmission is complete, bit STF in SCSR1 is cleared to 0 and bit IRRS1 in interrupt request register 2 (IRRS2) is set to 1. The selected TAIL MARK is output after the data transmission. During TAIL MARK output, bit MTRF in SCSR1 is set to 1. Data can be sent continuously by repeating steps 4 to 6. Check that SCI1 is in the idle state before rewriting bit MRKON in SCR1.
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Section 10 Serial Communication Interface
10.2.5
Interrupts
SCI1 can generate an interrupt at the end of a data transfer. When an SCI1 transfer is complete, bit IRRS1 in interrupt request register 2 (IRR2) is set to 1. SCI1 interrupt requests can be enabled or disabled by bit IENS1 of interrupt enable register 2 (IENR2). For further details, see section 3.3, Interrupts.
10.3
10.3.1
SCI3
Overview
Serial communication interface 3 (SCI3) can carry out serial data communication in either asynchronous or synchronous mode. It is also provided with a multiprocessor communication function that enables serial data to be transferred among processors. Features Features of SCI3 are listed below. * Choice of asynchronous or synchronous mode for serial data communication Asynchronous mode Serial data communication is performed asynchronously, with synchronization provided character by character. In this mode, serial data can be exchanged with standard asynchronous communication LSIs such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA). A multiprocessor communication function is also provided, enabling serial data communication among processors. There is a choice of 12 data transfer formats.
Data length Stop bit length Parity Multiprocessor bit Receive error detection Break detection 7 or 8 bits 1 or 2 bits Even, odd, or none "1" or "0" Parity, overrun, and framing errors Break detected by reading the RXD pin level directly when a framing error occurs
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Section 10 Serial Communication Interface
Synchronous mode Serial data communication is synchronized with a clock. In his mode, serial data can be exchanged with another LSI that has a synchronous communication function.
Data length Receive error detection 8 bits Overrun errors
* Full-duplex communication Separate transmission and reception units are provided, enabling transmission and reception to be carried out simultaneously. The transmission and reception units are both double-buffered, allowing continuous transmission and reception. * On-chip baud rate generator, allowing any desired bit rate to be selected * Choice of an internal or external clock as the transmit/receive clock source * Six interrupt sources: transmit end, transmit data empty, receive data full, overrun error, framing error, and parity error
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Section 10 Serial Communication Interface
Block Diagram Figure 10.6 shows a block diagram of SCI3.
SCK3
External clock
Internal clock (/64, /16, /4, ) Baud rate generator
BRC Clock
BRR
Transmit/receive control circuit
SCR3 SSR
TXD
TSR
TDR
RXD
RSR
RDR Interrupt request (TEI, TXI, RXI, ERI)
Legend: RSR: RDR: TSR: TDR: SMR: SCR3: SSR: BRR: BRC:
Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register Serial control register 3 Serial status register Bit rate register Bit rate counter
Figure 10.6 SCI3 Block Diagram
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Internal data bus
SMR
Section 10 Serial Communication Interface
Pin Configuration Table 10.4 shows the SCI3 pin configuration. Table 10.4 Pin Configuration
Name SCI3 clock SCI3 receive data input SCI3 transmit data output Abbr. SCK3 RXD TXD I/O I/O Input Output Function SCI3 clock input/output SCI3 receive data input SCI3 transmit data output
Register Configuration Table 10.5 shows the SCI3 register configuration. Table 10.5 Registers
Name Serial mode register Bit rate register Serial control register 3 Transmit data register Serial status register Receive data register Transmit shift register Receive shift register Bit rate counter Abbr. SMR BRR SCR3 TDR SSR RDR TSR RSR BRC R/W R/W R/W R/W R/W R/W R Initial Value H'00 H'FF H'00 H'FF H'84 H'00 Address H'FFA8 H'FFA9 H'FFAA H'FFAB H'FFAC H'FFAD
Protected Protected Protected
10.3.2
Register Descriptions
Receive Shift Register (RSR)
Bit 7 6 5 4 3 2 1 0
Read/Write

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Section 10 Serial Communication Interface
RSR is a register used to receive serial data. Serial data input to RSR from the RXD pin is set in the order in which it is received, starting from the LSB (bit 0), and converted to parallel data. When one byte of data is received, it is transferred to RDR automatically. RSR cannot be read or written directly by the CPU. Receive Data Register (RDR)
Bit Initial value Read/Write 7 RDR7 0 R 6 RDR6 0 R 5 RDR5 0 R 4 RDR4 0 R 3 RDR3 0 R 2 RDR2 0 R 1 RDR1 0 R 0 RDR0 0 R
RDR is an 8-bit register that stores received serial data. When reception of one byte of data is finished, the received data is transferred from RSR to RDR, and the receive operation is completed. RSR is then enabled for reception. RSR and RDR are double-buffered, allowing consecutive receive operations. RDR is a read-only register, and cannot be written by the CPU. RDR is initialized to H'00 upon reset, and in standby, watch, subactive, or subsleep mode. Transmit Shift Register (TSR)
Bit 7 6 5 4 3 2 1 0
Read/Write

TSR is a register used to transmit serial data. Transmit data is first transferred from TDR to TSR, and serial data transmission is carried out by sending the data to the TXD pin in order, starting from the LSB (bit 0). When one byte of data is transmitted, the next byte of transmit data is transferred from TDR to TSR, and transmission started, automatically. Data transfer from TDR to TSR is not performed if no data has been written to TDR (if bit TDRE is set to 1 in the serial status register (SSR)). TSR cannot be read or written directly by the CPU.
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Transmit Data Register (TDR)
Bit Initial value Read/Write 7 TDR7 1 R/W 6 TDR6 1 R/W 5 TDR5 1 R/W 4 TDR4 1 R/W 3 TDR3 1 R/W 2 TDR2 1 R/W 1 TDR1 1 R/W 0 TDR0 1 R/W
TDR is an 8-bit register that stores transmit data. When TSR is found to be empty, the transmit data written in TDR is transferred to TSR, and serial data transmission is started. Continuous transmission is possible by writing the next transmit data to TDR during TSR serial data transmission. TDR can be read or written by the CPU at any time. TDR is initialized to H'FF upon reset, and in standby, watch, subactive, or subsleep mode. Serial Mode Register (SMR)
Bit Initial value Read/Write 7 COM 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 PM 0 R/W 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W
SMR is an 8-bit register used to set the serial data transfer format and to select the clock source for the baud rate generator. SMR can be read or written by the CPU at any time. SMR is initialized to H'00 upon reset, and in standby, watch, subactive, or subsleep mode. Bit 7Communication Mode (COM): Bit 7 selects whether SCI3 operates in asynchronous mode or synchronous mode.
Bit 7: COM 0 1 Description Asynchronous mode Synchronous mode (initial value)
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Bit 6Character Length (CHR): Bit 6 selects either 7 or 8 bits as the data length to be used in asynchronous mode. In synchronous mode the data length is always 8 bits, irrespective of the bit 6 setting.
Bit 6: CHR 0 1 Note: * Description 8-bit data 7-bit data* When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted. (initial value)
Bit 5Parity Enable (PE): Bit 5 selects whether a parity bit is to be added during transmission and checked during reception in asynchronous mode. In synchronous mode parity bit addition and checking is not performed, irrespective of the bit 5 setting.
Bit 5: PE 0 1 Note: * Description Parity bit addition and checking disabled Parity bit addition and checking enabled* (initial value)
When PE is set to 1, even or odd parity, as designated by bit PM, is added to transmit data before it is sent, and the received parity bit is checked against the parity designated by bit PM.
Bit 4Parity Mode (PM): Bit 4 selects whether even or odd parity is to be used for parity addition and checking. The PM bit setting is only valid in asynchronous mode when bit PE is set to 1, enabling parity bit addition and checking. The PM bit setting is invalid in synchronous mode, and in asynchronous mode if parity bit addition and checking is disabled.
Bit 4: PM 0 1 Description Even parity* 2 Odd parity*
1
(initial value)
Notes: 1. When even parity is selected, a parity bit is added in transmission so that the total number of 1 bits in the transmit data plus the parity bit is an even number; in reception, a check is carried out to confirm that the number of 1 bits in the receive data plus the parity bit is an even number. 2. When odd parity is selected, a parity bit is added in transmission so that the total number of 1 bits in the transmit data plus the parity bit is an odd number; in reception, a check is carried out to confirm that the number of 1 bits in the receive data plus the parity bit is an odd number.
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Bit 3Stop Bit Length (STOP): Bit 3 selects 1 bit or 2 bits as the stop bit length is asynchronous mode. The STOP bit setting is only valid in asynchronous mode. When synchronous mode is selected the STOP bit setting is invalid since stop bits are not added.
Bit 3: STOP 0 1 Description 1 stop bit*
1
(initial value)
2 2 stop bits*
Notes: 1. In transmission, a single 1 bit (stop bit) is added at the end of a transmit character. 2. In transmission, two 1 bits (stop bits) are added at the end of a transmit character.
In reception, only the first of the received stop bits is checked, irrespective of the STOP bit setting. If the second stop bit is 1 it is treated as a stop bit, but if 0, it is treated as the start bit of the next transmit character. Bit 2Multiprocessor Mode (MP): Bit 2 enables or disables the multiprocessor communication function. When the multiprocessor communication function is enabled, the parity settings in the PE and PM bits are invalid. The MP bit setting is only valid in asynchronous mode. When synchronous mode is selected the MP bit should be set to 0. For details on the multiprocessor communication function, see section 10.3.6, Multiprocessor Communication Function.
Bit 2: MP 0 1 Description Multiprocessor communication function disabled Multiprocessor communication function enabled (initial value)
Bits 1 and 0Clock Select 1, 0 (CKS1, CKS0): Bits 1 and 0 choose /64, /16, /4, or as the clock source for the baud rate generator. For the relation between the clock source, bit rate register setting, and baud rate, see Bit Rate Register (BRR).
Bit 1: CKS1 0 1 Bit 0: CKS0 0 1 0 1 Description clock /4 clock /16 clock /64 clock (initial value)
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Serial Control Register 3 (SCR3)
Bit Initial value Read/Write 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W
SCR3 is an 8-bit register for selecting transmit or receive operation, the asynchronous mode clock output, interrupt request enabling or disabling, and the transmit/receive clock source. SCR3 can be read or written by the CPU at any time. SCR3 is initialized to H'00 upon reset, and in standby, watch, subactive, or subsleep mode. Bit 7Transmit interrupt Enable (TIE): Bit 7 selects enabling or disabling of the transmit data empty interrupt request (TXI) when transmit data is transferred from the transmit data register (TDR) to the transmit shift register (TSR), and bit TDRE in the serial status register (SSR) is set to 1. TXI can be released by clearing bit TDRE or bit TIE to 0.
Bit 7: TIE 0 1 Description Transmit data empty interrupt request (TXI) disabled Transmit data empty interrupt request (TXI) enabled (initial value)
Bit 6Receive Interrupt Enable (RIE): Bit 6 selects enabling or disabling of the receive data full interrupt request (RXI) and the receive error interrupt request (ERI) when receive data is transferred from the receive shift register (RSR) to the receive data register (RDR), and bit RDRF in the serial status register (SSR) is set to 1. There are three kinds of receive error: overrun, framing, and parity. RXI and ERI can be released by clearing bit RDRF or the FER, PER, or OER error flag to 0, or by clearing bit RIE to 0.
Bit 6: RIE 0 1 Description Receive data full interrupt request (RXI) and receive error interrupt request (ERI) disabled (initial value) Receive data full interrupt request (RXI) and receive error interrupt request (ERI) enabled
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Bit 5Transmit Enable (TE): Bit 5 selects enabling or disabling of the start of transmit operation.
Bit 5: TE 0 1 Description
1 3 Transmit operation disabled* (TXD pin is transmit data pin)* 2 3 Transmit operation enabled* (TXD pin is transmit data pin)*
(initial value)
Notes: 1. Bit TDRE in SSR is fixed at 1. 2. When transmit data is written to TDR in this state, bit TDR in SSR is cleared to 0 and serial data transmission is started. Be sure to carry out serial mode register (SMR) settings to decide the transmission format before setting bit TE to 1. 3. When bit TXD in PMR7 is set to 1. When bit TXD is cleared to 0, the TXD pin functions as an I/O port regardless of the TE bit setting.
Bit 4Receive Enable (RE): Bit 4 selects enabling or disabling of the start of receive operation.
Bit 4: RE 0 1 Description Receive operation disabled* (RXD pin is I/O port) 2 Receive operation enabled* (RXD pin is receive data pin)
1
(initial value)
Notes: 1. Note that the RDRF, FER, PER, and OER flags in SSR are not affected when bit RE is cleared to 0, and retain their previous state. 2. In this state, serial data reception is started when a start bit is detected in asynchronous mode or serial clock input is detected in synchronous mode. Be sure to carry out serial mode register (SMR) settings to decide the reception format before setting bit RE to 1.
Bit 3Multiprocessor Interrupt Enable (MPIE): Bit 3 selects enabling or disabling of the multiprocessor interrupt request. The MPIE bit setting is only valid when asynchronous mode is selected and reception is carried out with bit MP in SMR set to 1. The MPIE bit setting is invalid when bit COM is set to 1 or bit MP is cleared to 0.
Bit 3: MPIE 0 Description Multiprocessor interrupt request disabled (normal receive operation) (initial value) Clearing condition: When data is received in which the multiprocessor bit is set to 1 Multiprocessor interrupt request enabled* * Receive data transfer from RSR to RDR, receive error detection, and setting of the RDRF, FER, and OER status flags in SSR is not performed. RXI, ERI, and setting of the RDRF, FER, and OER flags in SSR, are disabled until data with the multiprocessor bit set to 1 is received. When a receive character with the multiprocessor bit set to 1 is received, bit MPBR in SSR is set to 1, bit MPIE is automatically cleared to 0, and RXI and ERI requests (when bits TIE and RIE in serial control register (SCR) are set to 1) and setting of the RDRF, FER, and OER flags are enabled.
1 Note:
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Bit 2Transmit End Interrupt Enable (TEIE): Bit 2 selects enabling or disabling of the transmit end interrupt request (TEI) if there is no valid transmit data in TDR when MSB data is to be sent.
Bit 2: TEIE 0 1 Note: * Description Transmit end interrupt request (TEI) disabled Transmit end interrupt request (TEI) enabled* (initial value)
TEI can be released by clearing bit TDRE to 0 and clearing bit TEND to 0 in SSR, or by clearing bit TEIE to 0.
Bits 1 and 0Clock Enable 1 and 0 (CKE1, CKE0): Bits 1 and 0 select the clock source and enabling or disabling of clock output from the SCK3 pin. These bits determine whether the SCK3 pin functions as an I/O port, a clock output pin, or a clock input pin. The CKE0 bit setting is only valid in case of internal clock operation (CKE1 = 0) in asynchronous mode. In synchronous mode, or when external clock operation is used (CKE1 = 1), bit CKE0 should be cleared to 0. After setting bits CKE1 and CKE0, set the operating mode in the serial mode register (SMR). For details on clock source selection, see table 10.10 in 10.3.3, Operation.
Description Bit 1: CKE1 0 Bit 0: CKE0 0 1 1 0 1 Communication Mode Asynchronous Synchronous Asynchronous Synchronous Asynchronous Synchronous Asynchronous Synchronous Clock Source Internal clock Internal clock Internal clock Reserved External clock External clock Reserved Reserved Clock input*
3
SCK3 Pin Function I/O port*
1 1
Serial clock output* 2 Clock output*
Serial clock input
Notes: 1. Initial value 2. A clock with the same frequency as the bit rate is output. 3. Input a clock with a frequency 16 times the bit rate.
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Serial Status Register (SSR)
Bit Initial value Read/Write Note: * 7 TDRE 1 R/(W)* 6 RDRF 0 R/(W)* 5 OER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPBR 0 R 0 MPBT 0 R/W
Only a write of 0 for flag clearing is possible.
SSR is an 8-bit register containing status flags that indicate the operational status of SCI3, and multiprocessor bits. SSR can be read or written by the CPU at any time, but only a write of 1 is possible to bits TDRE, RDRF, OER, PER, and FER. In order to clear these bits by writing 0, 1 must first be read. Bits TEND and MPBR are read-only bits, and cannot be modified. SSR is initialized to H'84 upon reset, and in standby, watch, subactive, or subsleep mode. Bit 7Transmit Data Register Empty (TDRE): Bit 7 indicates that transmit data has been transferred from TDR to TSR.
Bit 7: TDRE 0 Description Transmit data written in TDR has not been transferred to TSR Clearing conditions: * After reading TDRE = 1, cleared by writing 0 to TDRE * 1 When data is written to TDR by an instruction Transmit data has not been written to TDR, or transmit data written in TDR has been transferred to TSR Setting conditions: * When bit TE in SCR3 is cleared to 0 * When data is transferred from TDR to TSR (initial value)
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Bit 6Receive Data Register Full (RDRF): Bit 6 indicates that received data is stored in RDR.
Bit 6: RDRF 0 Description There is no receive data in RDR Clearing conditions: * After reading RDRF = 1, cleared by writing 0 to RDRF * 1 When RDR data is read by an instruction There is receive data in RDR Setting condition: When reception ends normally and receive data is transferred from RSR to RDR Note: If an error is detected in the receive data, or if the RE bit in SCR3 has been cleared to 0, RDR and bit RDRF are not affected and retain their previous state. Note that if data reception is completed while bit RDRF is still set to 1, an overrun error (OER) will result and the receive data will be lost. (initial value)
Bit 5Overrun Error (OER): Bit 5 indicates that an overrun error has occurred during reception.
Bit 5: OER 0 Description Reception in progress or completed*
1
(initial value)
1
Clearing condition: After reading OER = 1, cleared by writing 0 to OER 2 An overrun error has occurred during reception* Setting condition: When reception is completed with RDRF set to 1
Notes: 1. When bit RE in SCR3 is cleared to 0, bit OER is not affected and retains its previous state. 2. RDR retains the receive data it held before the overrun error occurred, and data received after the error is lost. Reception cannot be continued with bit OER set to 1, and in synchronous mode, transmission cannot be continued either.
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Bit 4Framing Error (FER): Bit 4 indicates that a framing error has occurred during reception in asynchronous mode.
Bit 4: FER 0 Description Reception in progress or completed*
1
(initial value)
1
Clearing condition: After reading FER = 1, cleared by writing 0 to FER 2 A framing error has occurred during reception* Setting condition: When the stop bit at the end of the receive data is checked for a value of 1 at 2 the end of reception, and the stop bit is 0*
Notes: 1. When bit RE in SCR3 is cleared to 0, bit FER is not affected and retains its previous state. 2. Note that, in 2-stop-bit mode, only the first stop bit is checked for a value of 1, and the second stop bit is not checked. When a framing error occurs the receive data is transferred to RDR but bit RDRF is not set. Reception cannot be continued with bit FER set to 1. In synchronous mode, neither transmission nor reception is possible when bit FER is set to 1.
Bit 3Parity Error (PER): Bit 3 indicates that a parity error has occurred during reception with parity added in asynchronous mode.
Bit 3: PER 0 Description Reception in progress or completed*
1
(initial value)
1
Clearing condition: After reading PER = 1, cleared by writing 0 to PER 2 A parity error has occurred during reception* Setting condition: When the number of 1 bits in the receive data plus parity bit does not match the parity designated by bit PM in the serial mode register (SMR)
Notes: 1. When bit RE in SCR3 is cleared to 0, bit PER is not affected and retains its previous state. 2. Receive data in which it a parity error has occurred is still transferred to RDR, but bit RDRF is not set. Reception cannot be continued with bit PER set to 1. In synchronous mode, neither transmission nor reception is possible when bit PER is set to 1.
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Bit 2Transmit End (TEND): Bit 2 indicates that bit TDRE is set to 1 when the last bit of a transmit character is sent. Bit 2 is a read-only bit and cannot be modified.
Bit 2: TEND 0 Description Transmission in progress Clearing conditions: * After reading TDRE = 1, cleared by writing 0 to TDRE * 1 When data is written to TDR by an instruction (initial value) Transmission ended Setting conditions: * When bit TE in SCR3 is cleared to 0 * When bit TDRE is set to 1 when the last bit of a transmit character is sent
Bit 1Multiprocessor Bit Receive (MPBR): Bit 1 stores the multiprocessor bit in a receive character during multiprocessor format reception in asynchronous mode. Bit 1 is a read-only bit and cannot be modified.
Bit 1: MPBR 0 1 Note: * Description Data in which the multiprocessor bit is 0 has been received* Data in which the multiprocessor bit is 1 has been received When bit RE is cleared to 0 in SCR3 with the multiprocessor format, bit MPBR is not affected and retains its previous state. (initial value)
Bit 0Multiprocessor Bit Transfer (MPBT): Bit 0 stores the multiprocessor bit added to transmit data when transmitting in asynchronous mode. The bit MPBT setting is invalid when synchronous mode is selected, when the multiprocessor communication function is disabled, and when not transmitting.
Bit 0: MPBT 0 1 Description A 0 multiprocessor bit is transmitted A 1 multiprocessor bit is transmitted (initial value)
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Bit Rate Register (BRR)
Bit Initial value Read/Write 7 BRR7 1 R/W 6 BRR6 1 R/W 5 BRR5 1 R/W 4 BRR4 1 R/W 3 BRR3 1 R/W 2 BRR2 1 R/W 1 BRR1 1 R/W 0 BRR0 1 R/W
BRR is an 8-bit register that designates the transmit/receive bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 of the serial mode register (SMR). BRR can be read or written by the CPU at any time. BRR is initialized to H'FF upon reset, and in standby, watch, subactive, or subsleep mode. Table 10.6 shows examples of BRR settings in asynchronous mode. The values shown are for active (high-speed) mode. Table 10.6 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode)
OSC (MHz) 2 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 1 0 0 0 0 0 0 N 70 207 103 51 25 12 0 Error (%) +0.03 +0.16 +0.16 +0.16 +0.16 +0.16 0 n 1 0 0 0 0 0 0 0 0 0 2.4576 N 86 255 127 63 31 15 7 3 1 0 Error (%) +0.31 0 0 0 0 0 0 0 0 0 n 1 1 0 0 0 0 0 0 N 141 103 207 103 51 25 12 1 4 Error (%) +0.03 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 0 n 1 1 0 0 0 0 0 0 4.194304 N 148 108 217 108 54 26 13 6 Error (%) -0.04 +0.21 +0.21 +0.21 -0.70 +1.14 -2.48 -2.48
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Section 10 Serial Communication Interface OSC (MHz) 4.9152 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 1 1 0 0 0 0 0 0 0 0 N 174 127 255 127 63 31 15 7 3 1 Error (%) -0.26 0 0 0 0 0 0 0 0 0 n 1 1 1 0 0 0 0 0 0 0 OSC (MHz) 9.8304 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 1 1 0 0 0 0 0 0 0 0 N 86 255 127 255 127 63 31 15 7 4 3 Error (%) +0.31 0 0 0 0 0 0 0 0 -1.70 0 n 2 2 1 1 0 0 0 0 0 0 0 N 88 64 129 64 129 64 32 15 7 4 3 10 Error (%) -0.25 +0.16 +0.16 +0.16 +0.16 +0.16 -1.36 +1.73 +1.73 0 +1.73 N 212 155 77 155 77 38 19 9 4 2 6 Error (%) +0.03 +0.16 +0.16 +0.16 +0.16 +0.16 -2.34 -2.34 -2.34 0 n 2 1 1 0 0 0 0 0 0 0 7.3728 N 64 191 95 191 95 47 23 11 5 2 Error (%) +0.70 0 0 0 0 0 0 0 0 0 n 2 1 1 0 0 0 0 0 0 N 70 207 103 207 103 51 25 12 3 8 Error (%) +0.03 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 0
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Notes: 1. The setting should be made so that the error is not more than 1%. 2. The value set in BRR is given by the following equation:
N= OSC x 106 - 1 (64 x 22n x B)
where B: N: OSC: n: Bit rate (bit/s) Baud rate generator BRR setting (0 N 255) Value of OSC (MHz) Baud rate generator input clock number (n = 0, 1, 2, or 3) (The relation between n and the clock is shown in table 10.7.)
Table 10.7 Relation between n and Clock
SMR Setting n 0 1 2 3 Clock /4 16 /64 CKS1 0 0 1 1 CKS0 0 1 0 1
3. The error in table 10.6 is the value obtained from the following equation, rounded to two decimal places.
Error (%) = B (rate obtained from n, N, OSC) - R (bit rate in left-hand column in table 10.6) x 100 R (bit rate in left-hand column in table 10.6)
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Table 10.8 shows the maximum bit rate for each frequency. The values shown are for active (highspeed) mode. Table 10.8 Maximum Bit Rate for Each Frequency (Asynchronous Mode)
Setting OSC (MHz) 2 2.4576 4 4.194304 4.9152 6 7.3728 8 9.8304 10 Maximum Bit Rate (bits/s) 31250 38400 62500 65536 76800 93750 115200 125000 153600 156250 n 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0
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Table 10.9 shows examples of BRR settings in synchronous mode. The values shown are for active (high-speed) mode. Table 10.9 Examples of BRR Settings for Various Bit Rates (Synchronous Mode)
OSC (MHz) Bit Rate (bits/s) 110 250 500 1k 2.5 k 5k 10 k 25 k 50 k 100 k 250 k 500 k 1M 2.5 M Legend: Blank: Cannot be set. : A setting can be made, but an error will result. *: Continuous transmission/reception is not possible. 2 n 1 1 0 0 0 0 0 0 0 N 249 124 249 99 49 24 9 4 0* n 2 1 1 0 0 0 0 0 0 0 0 4 N 124 249 124 199 99 49 19 9 4 1 0* n 2 2 1 1 0 0 0 0 0 0 0 0 8 N 249 124 249 99 199 99 39 19 9 3 1 0* n 1 0 0 0 0 0 10 N 124 249 124 49 24 4
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Note: The value set in BRR is given by the following equation:
N= OSC x 106 - 1 (8 x 22n x B)
where B: N: OSC: n:
Bit rate (bit/s) Baud rate generator BRR setting (0 N 255) Value of OSC (MHz) Baud rate generator input clock number (n = 0, 1, 2, or 3) (The relation between n and the clock is shown in table 10.10.)
Table 10.10 Relation between n and Clock
SMR Setting n 0 1 2 3 Clock /4 16 /64 CKS1 0 0 1 1 CKS0 0 1 0 1
10.3.3
Operation
SCI3 can perform serial communication in two modes: asynchronous mode in which synchronization is provided character by character, and synchronous mode in which synchronization is provided by clock pulses. The serial mode register (SMR) is used to select asynchronous or synchronous mode and the data transfer format, as shown in table 10.11. The clock source for SCI3 is determined by bit COM in SMR and bits CKE1 and CKE0 in SCR3, as shown in table 10.12. Asynchronous Mode * Choice of 7- or 8-bit data length * Choice of parity addition, multiprocessor bit addition, and addition of 1 or 2 stop bits. (The combination of these parameters determines the data transfer format and the character length.) * Framing error (FER), parity error (PER), overrun error (OER), and break detection during reception
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* Choice of internal or external clock as the clock source When internal clock is selected: SCI3 operates on the baud rate generator clock, and a clock with the same frequency as the bit rate can be output. When external clock is selected: A clock with a frequency 16 times the bit rate must be input. (The on-chip baud rate generator is not used.) Synchronous Mode * Data transfer format: Fixed 8-bit data length * Overrun error (OER) detection during reception * Choice of internal or external clock as the clock source When internal clock is selected: SCI3 operates on the baud rate generator clock, and a serial clock is output. When external clock is selected: The on-chip baud rate generator is not used, and SCI3 operates on the input serial clock. Table 10.11 SMR Settings and Corresponding Data Transfer Formats
SMR Setting Bit 7: Bit 6: Bit 2: Bit 5: Bit 3: COM CHR MP PE STOP Mode 0 0 0 0 1 1 0 1 0 1 1 * 0 1 * * * * * 0 1 0 1 0 1 0 1 0 1 0 1 * Synchronous mode 8-bit data No No Asynchronous 8-bit data mode (multiprocessor 7-bit data format) Yes No Yes 7-bit data No Asynchronous mode Communication Format MultiproData Length cessor Bit 8-bit data No Parity Stop Bit Bit Length No Yes 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits No
Legend: * Don't care
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Table 10.12 SMR and SCR3 Settings and Clock Source Selection
SMR Bit 7: COM 0 SCR3 Bit 1: CKE1 0 Bit 0: CKE0 0 1 1 1 0 1 1 0 1 1 0 1 0 0 0 1 1 1 Synchronous mode Mode Asynchronous mode Clock Source Internal Transmit/Receive Clock SCK3 Pin Function I/O port (SCK3 pin not used) Outputs clock with same frequency as bit rate External Internal External Inputs clock with frequency 16 times bit rate Outputs serial clock Inputs serial clock
Reserved (Do not specify these combinations)
Interrupts and Continuous Transmission/Reception: SCI3 can carry out continuous reception using RXI and continuous transmission using TXI. These interrupts are shown in table 10.13. Table 10.13 Transmit/Receive Interrupts
Interrupt RXI Flags RDRF RIE Interrupt Request Conditions When serial reception is performed normally and receive data is transferred from RSR to RDR, bit RDRF is set to 1, and if bit RIE is set to 1 at this time, RXI is enabled and an interrupt is requested. (See figure 10.7 (a).) When TSR is found to be empty (on completion of the previous transmission) and the transmit data placed in TDR is transferred to TSR, bit TDRE is set to 1. If bit TIE is set to 1 at this time, TXI is enabled and an interrupt is requested. (See figure 10.7 (b).) When the last bit of the character in TSR is transmitted, if bit TDRE is set to 1, bit TEND is set to 1. If bit TEIE is set to 1 at this time, TEI is enabled and an interrupt is requested. (See figure 10.7 (c).) Notes The RXI interrupt routine reads the receive data transferred to RDR and clears bit RDRF to 0. Continuous reception can be performed by repeating the above operations until reception of the next RSR data is completed. The TXI interrupt routine writes the next transmit data to TDR and clears bit TDRE to 0. Continuous transmission can be performed by repeating the above operations until the data transferred to TSR has been transmitted. TEI indicates that the next transmit data has not been written to TDR when the last bit of the transmit character in TSR is sent.
TXI
TDRE TIE
TEI
TEND TEIE
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RDR RDR RSR (reception completed, transfer) RXD pin RDRF = 0 RDRF 1 (RXI request when RIE = 1)
RSR (reception in progress) RXD pin
Figure 10.7 (a) RDRF Setting and RXI Interrupt
TDR (next transmit data) TDR TSR (transmission completed, transfer) TXD pin TDRE = 0 TDRE 1 (TXI request when TIE = 1)
TSR (transmission in progress) TXD pin
Figure 10.7 (b) TDRE Setting and TXI Interrupt
TDR TDR TSR (transmission in progress) TXD pin TEND = 0 TXD pin TEND 1 (TEI request when TEIE = 1) TSR (reception completed)
Figure 10.7 (c) TEND Setting and TEI Interrupt
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10.3.4
Operation in Asynchronous Mode
In asynchronous mode, serial communication is performed with synchronization provided character by character. A start bit indicating the start of communication and one or two stop bits indicating the end of communication are added to each character before it is sent. SCI3 has separate transmission and reception units, allowing full-duplex communication. As the transmission and reception units are both double-buffered, data can be written during transmission and read during reception, making possible continuous transmission and reception. Data Transfer Format: The general data transfer format in asynchronous communication is shown in figure 10.8.
(LSB) Serial data Start bit Transmit/receive data (MSB) Parity bit Stop bit(s) 1 Mark state
1 bit
7 or 8 bits
1 bit or none
1 or 2 bits
One transfer data unit (character or frame)
Figure 10.8 Data Format in Asynchronous Communication In asynchronous communication, the communication line is normally in the mark state (high level). SCI3 monitors the communication line and when it detects a space (low level), identifies this as a start bit and begins serial data communication. One transfer data character consists of a start bit (low level), followed by transmit/receive data (LSB-first format, starting from the least significant bit), a parity bit (high or low level), and finally one or two stop bits (high level). In asynchronous mode, synchronization is performed by the falling edge of the start bit during reception. The data is sampled on the 8th pulse of a clock with a frequency 16 times the bit period, so that the transfer data is latched at the center of each bit.
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Table 10.14 shows the 12 data transfer formats that can be set in asynchronous mode. The format is selected by the settings in the serial mode register (SMR). Table 10.14 Data Transfer Formats (Asynchronous Mode)
SMR Settings CHR 0 0 0 0 1 1 1 1 0 0 1 1 PE 0 0 1 1 0 0 1 1 * * * * MP 0 0 0 0 0 0 0 0 1 1 1 1 STOP 0 1 0 1 0 1 0 1 0 1 0 1 1 S S S S S S S S S S S S Serial Data Transfer Format and Frame Length 2 3 4 5 6 7 8 9 10
STOP
11
12
8-bit data 8-bit data 8-bit data 8-bit data 7-bit data 7-bit data 7-bit data 7-bit data 8-bit data 8-bit data 7-bit data 7-bit data
STOP
STOP STOP
P P
STOP
STOP STOP
STOP STOP
P P
STOP
STOP STOP
MPB STOP
MPB STOP STOP
MPB STOP
MPB STOP STOP
Legend: S: Start bit STOP: Stop bit P: Parity bit MPB: Multiprocessor bit *: Don't care
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Clock: Either an internal clock generated by the baud rate generator or an external clock input at the SCK3 pin can be selected as the SCI3 transmit/receive clock. The selection is made by means of bit COM in SMR and bits CKE1 and CKE0 in SCR3. See table 10.12 for details on clock source selection. When an external clock is input at the SCK3 pin, a clock with a frequency of 16 times the bit rate used should be input. When SCI3 operates on an internal clock, the clock can be output at the SCK3 pin. In this case the frequency of the output clock is the same as the bit rate, and the phase is such that the clock rises at the center of each bit of transmit/receive data, as shown in figure 10.9.
Clock Serial data 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1
1 character (1 frame)
Figure 10.9 Phase Relationship between Output Clock and Transfer Data (Asynchronous Mode) (8-Bit Data, Parity, 2 Stop Bits) Data Transfer Operations SCI3 Initialization: Before data is transferred on SCI3, bits TE and RE in SCR3 must first be cleared to 0, and then SCI3 must be initialized as follows. Note: If the operation mode or data transfer format is changed, bits TE and RE must first be cleared to 0. When bit TE is cleared to 0, bit TDRE is set to 1. Note that the RDRF, PER, FER, and OER flags and the contents of RDR are retained when RE is cleared to 0. When an external clock is used in asynchronous mode, the clock should not be stopped during operation, including initialization. When an external clock is used in synchronous mode, the clock should not be supplied during operation, including initialization.
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Section 10 Serial Communication Interface
Figure 10.10 shows an example of a flowchart for initializing SCI3.
Start
Clear bits TE and RE to 0 in SCR3
1
Set bits CKE1 and CKE0
2
Set data transfer format in SMR
1. Set clock selection in SCR3. Be sure to clear the other bits to 0. If clock output is selected in asynchronous mode, the clock is output immediately after setting bits CKE1 and CKE0. If clock output is selected for reception in synchronous mode, the clock is output immediately after bits CKE1, CKE0, and RE are set to 1. 2. Set the data transfer format in the serial mode register (SMR). 3. Write the value corresponding to the transfer rate in BRR. This operation is not necessary when an external clock is selected. 4. Wait for at least the interval required to transmit or receive one bit, then set TE or RE in the serial control register (SCR3). Setting RE enables the RxD pin to be used, and when transmitting, setting bit TXD in PMR7 enables the TXD output pin to be used. Also set the RIE, TIE, TEIE, and MPIE bits as necessary to enable interrupts. The initial states are the mark transmit state and the idle receive state (waiting for a start bit).
3
Set value in BRR Wait No
Has 1-bit period elapsed? Yes
4
Set bit TE or RE to 1 in SCR3, set bits RIE, TIE, TEIE, and MPIE as necessary, and when transmitting (TE = 1), set bit TXD to 1 in PMR7
End
Figure 10.10 Example of SCI3 Initialization Flowchart
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Section 10 Serial Communication Interface
Transmitting: Figure 10.11 shows an example of a flowchart for data transmission. This procedure should be followed for data transmission after initializing SCI3.
Start
1
Read bit TDRE in SSR
No TDRE = 1? Yes Write transmit data to TDR
1. Read the serial status register (SSR) and check that bit TDRE is set to 1, then write transmit data to the transmit data register (TDR). When data is written to TDR, bit TDRE is cleared to 0 automatically. 2. When continuing data transmission, be sure to read TDRE = 1 to confirm that a write can be performed before writing data to TDR. When data is written to TDR, bit TDRE is cleared to 0 automatically.
2
Continue data transmission? No Read bit TEND in SSR
Yes
3. If a break is to be output when data transmission ends, set the port PCR to 1 and clear the port PDR to 0, then clear bit TXD in PMR7 and bit TE in SCR3 to 0.
TEND = 1? Yes 3
No
Break output? Yes Set PDR = 0, PCR = 1
No
Clear bit TE to 0 in SCR3
End
Figure 10.11 Example of Data Transmission Flowchart (Asynchronous Mode)
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SCI3 operates as follows when transmitting data. SCI3 monitors bit TDRE in SSR, and when it is cleared to 0, recognizes that data has been written to TDR and transfers data from TDR to TSR. It then sets bit TDRE to 1 and starts transmitting. If bit TIE in SCR3 is set to 1 at this time, a TXI request is made. Serial data is transmitted from the TXD pin using the relevant data transfer format in table 10.14. When the stop bit is sent, SCI3 checks bit TDRE. If bit TDRE is cleared to 0, SCI3 transfers data from TDR to TSR, and when the stop bit has been sent, starts transmission of the next frame. If bit TDRE is set to 1, bit TEND in SSR is set to 1, and the mark state, in which 1s are transmitted, is established after the stop bit has been sent. If bit TEIE in SCR3 is set to 1 at this time, a TEI request is made. Figure 10.12 shows an example of the operation when transmitting in asynchronous mode.
Start bit Serial data 1 0 D0 D1 1 frame Transmit data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 Transmit data D1 1 frame D7 Parity Stop bit bit 0/1 1 Mark state 1
TDRE TEND LSI TXI request operation User processing TDRE cleared to 0 Data written to TDR TXI request TEI request
Figure 10.12 Example of Operation when Transmitting in Asynchronous Mode (8-Bit Data, Parity, 1 Stop Bit)
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Receiving: Figure 10.13 shows an example of a flowchart for data reception. This procedure should be followed for data reception after initializing SCI3.
Start
1
Read bits OER, PER, FER in SSR
OER + PER + FER = 1? No 2 Read bit RDRF in SSR
Yes
1. Read bits OER, PER, and FER in the serial status register (SSR) to determine if there is an error. If a receive error has occurred, execute receive error processing. 2. Read SSR and check that bit RDRF is set to 1. If it is, read the receive data in RDR. When the RDR data is read, bit RDRF is cleared to 0 automatically. 3. When continuing data reception, finish reading of bit RDRF and RDR before receiving the stop bit of the current frame. When the data in RDR is read, bit RDRF is cleared to 0 automatically.
RDRF = 1? Yes Read receive data in RDR
No
4
Receive error processing
4. If a receive error has occurred, read bits OER, PER, and FER in SSR to identify the error, and after carrying out the necessary error processing, ensure that bits OER, PER, and FER are all cleared to 0. Reception cannot be resumed if any of these bits is set to 1. In the case of a framing error, a break can be detected by reading the value of the RXD pin.4.
3
Continue data reception? No
Yes
(A) Clear bit RE to 0 in SCR3
End
Figure 10.13 Example of Data Reception Flowchart (Asynchronous Mode)
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4. If a receive error has occurred, read bits OER, PER, and FER in SSR to identify the error, and after carrying out the necessary error processing, ensure that bits OER, PER, and FER are all cleared to 0. Yes Reception cannot be resumed if any of these bits is set to 1. In the case of a framing error, a break can be detected by reading the value of the RXD pin.
4
Start receive error processing Overrun error processing OER = 1? No FER = 1? No PER = 1? No Clear bits OER, PER, FER to 0 in SSR Parity error processing Yes Framing error processing Yes Yes
Break? No
(A)
End of receive error processing
Figure 10.13 Example of Data Reception Flowchart (Asynchronous Mode) (cont) SCI3 operates as follows when receiving data. SCI3 monitors the communication line, and when it detects a 0 start bit, performs internal synchronization and begins reception. Reception is carried out in accordance with the relevant data transfer format in table 10.14. The received data is first placed in RSR in LSB-to-MSB order, and then the parity bit and stop bit(s) are received. SCI3 then carries out the following checks. * Parity check SCI3 checks that the number of 1 bits in the receive data conforms to the parity (odd or even) set in bit PM in the serial mode register (SMR). * Stop bit check SCI3 checks that the stop bit is 1. If two stop bits are used, only the first is checked. * Status check SCI3 checks that bit RDRF is set to 1, indicating that the receive data can be transferred from RSR to RDR.
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If no receive error is found in the above checks, bit RDRF is set to 1, and the receive data is stored in RDR. If bit RIE is set to 1 in SCR3, an RXI interrupt is requested. If the error checks identify a receive error, bit OER, PER, or FER is set to 1 depending on the kind of error. Bit RDRF retains its state prior to receiving the data. If bit RIE is set to 1 in SCR3, an ERI interrupt is requested. Table 10.15 shows the conditions for detecting a receive error, and receive data processing. Note: No further receive operations are possible while a receive error flag is set. Bits OER, FER, PER, and RDRF must therefore be cleared to 0 before resuming reception. Table 10.15 Receive Error Detection Conditions and Receive Data Processing
Receive Error Overrun error Abbreviation OER Detection Conditions When the next date receive operation is completed while bit RDRF is still set to 1 in SSR When the stop bit is 0 When the parity (odd or even) set in SMR is different from that of the received data Received Data Processing Receive data is not transferred from RSR to RDR Receive data is transferred from RSR to RDR Receive data is transferred from RSR to RDR
Framing error Parity error
FER PER
Figure 10.14 shows an example of the operation when receiving in asynchronous mode.
Start bit Serial data 1 0 D0 D1 1 frame Receive data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 Receive data D1 1 frame D7 Parity Stop bit bit 0/1 0 Mark state (idle state) 1
RDRF FER LSI operation User processing RXI request RDRF cleared to 0 RDR data read 0 start bit detected ERI request in response to framing error Framing error processing
Figure 10.14 Example of Operation when Receiving in Asynchronous Mode (8-Bit Data, Parity, 1 Stop Bit)
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10.3.5
Operation in Synchronous Mode
In synchronous mode, SCI3 transmits and receives data in synchronization with clock pulses. This mode is suitable for high-speed serial communication. SCI3 has separate transmission and reception units, allowing full-duplex communication with a shared clock. As the transmission and reception units are both double-buffered, data can be written during transmission and read during reception, making possible continuous transmission and reception. Data Transfer Format: The general data transfer format in synchronous communication is shown in figure 10.15.
* Serial clock LSB Serial data Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Bit 7
*
Don't care
8 bits One transfer data unit (character or frame)
Don't care
Note: * High level except in continuous transmission/reception
Figure 10.15 Data Format in Synchronous Communication In synchronous communication, data on the communication line is output from one falling edge of the serial clock until the next falling edge. Data confirmation is guaranteed at the rising edge of the serial clock. One transfer data character begins with the LSB and ends with the MSB. After output of the MSB, the communication line retains the MSB state. When receiving in synchronous mode, SCI3 latches receive data at the rising edge of the serial clock. The data transfer format uses a fixed 8-bit data length. Parity and multiprocessor bits cannot be added.
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Clock: Either an internal clock generated by the baud rate generator or an external clock input at the SCK3 pin can be selected as the SCI3 serial clock. The selection is made by means of bit COM in SMR and bits CKE1 and CKE0 in SCR3. See table 10.12 for details on clock source selection. When SCI3 operates on an internal clock, the serial clock is output at the SCK3 pin. Eight pulses of the serial clock are output in transmission or reception of one character, and when SCI3 is not transmitting or receiving, the clock is fixed at the high level. Data Transfer Operations SCI3 Initialization: Data transfer on SCI3 first of all requires that SCI3 be initialized as described in 10.3.4, SCI3 Initialization, and shown in figure 10.10. Transmitting: Figure 10.16 shows an example of a flowchart for data transmission. This procedure should be followed for data transmission after initializing SCI3.
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Start 1. Read the serial status register (SSR) and check that bit TDRE is set to 1, then write transmit data to the transmit data register (TDR). When data is written to TDR, bit TDRE is cleared to 0 automatically, the clock is output, and data transmission is started. 2. When continuing data transmission, be sure to read TDRE = 1 to confirm that a write can be performed before writing data to TDR. When data is written to TDR, bit TDRE is cleared to 0 automatically.
1
Read bit TDRE in SSR
No TDRE = 1? Yes Write transmit data to TDR
2
Continue data transmission? No Read bit TEND in SSR
Yes
TEND = 1? Yes Clear bit TE to 0 in SCR3
No
End
Figure 10.16 Example of Data Transmission Flowchart (Synchronous Mode) SCI3 operates as follows when transmitting data. SCI3 monitors bit TDRE in SSR, and when it is cleared to 0, recognizes that data has been written to TDR and transfers data from TDR to TSR. It then sets bit TDRE to 1 and starts transmitting. If bit TIE in SCR3 is set to 1 at this time, a TXI request is made.
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When clock output mode is selected, SCI3 outputs 8 serial clock pulses. When an external clock is selected, data is output in synchronization with the input clock. Serial data is transmitted from the TXD pin in order from the LSB (bit 0) to the MSB (bit 7). When the MSB (bit 7) is sent, checks bit TDRE. If bit TDRE is cleared to 0, SCI3 transfers data from TDR to TSR, and starts transmission of the next frame. If bit TDRE is set to 1, SCI3 sets bit TEND to 1 in SSR, and after sending the MSB (bit 7), retains the MSB state. If bit TEIE in SCR3 is set to 1 at this time, a TEI request is made. After transmission ends, the SCK3 pin is fixed at the high level. Note: Transmission is not possible if an error flag (OER, FER, or PER) that indicates the data reception status is set to 1. Check that these error flags (OER, FER, and PER) are all cleared to 0 before a transmit operation. Figure 10.17 shows an example of the operation when transmitting in synchronous mode.
Serial clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
1 frame TDRE TEND LSI TXI request operation User processing TDRE cleared to 0 Data written to TDR TXI request
1 frame
TEI request
Figure 10.17 Example of Operation when Transmitting in Synchronous Mode
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Section 10 Serial Communication Interface
Receiving: Figure 10.18 shows an example of a flowchart for data reception. This procedure should be followed for data reception after initializing SCI3.
Start
1
Read bit OER in SSR
1. Read bit OER in the serial status register (SSR) to determine if there is an error. If an overrun error has occurred, execute overrun error processing. Yes 2. Read SSR and check that bit RDRF is set to 1. If it is, read the receive data in RDR. When the RDR data is read, bit RDRF is cleared to 0 automatically. 3. When continuing data reception, finish reading of bit RDRF and RDR before receiving the MSB (bit 7) of the current frame. When the data in RDR is read, bit RDRF is cleared to 0 automatically. 4. If an overrun error has occurred, read bit OER in SSR, and after carrying out the necessary error processing, clear bit OER to 0. Reception cannot be resumed if bit OER is set to 1. Overrun error processing
OER = 1? No 2 Read bit RDRF in SSR
RDRF = 1? Yes Read receive data in RDR
No
4
3
Continue data reception? No Clear bit RE to 0 in SCR3
Yes
4
Start overrun error processing
End
Overrun error processing
Clear bit OER to 0 in SSR
End of overrun error processing
Figure 10.18 Example of Data Reception Flowchart (Synchronous Mode)
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Section 10 Serial Communication Interface
SCI3 operates as follows when receiving data. SCI3 performs internal synchronization and begins reception in synchronization with the serial clock input or output. The received data is placed in RSR in LSB-to-MSB order. After the data has been received, SCI3 checks that bit RDRF is set to 0, indicating that the receive data can be transferred from RSR to RDR. If this check shows that there is no overrun error, bit RDRF is set to 1, and the receive data is stored in RDR. If bit RIE is set to 1 in SCR3, an RXI interrupt is requested. If the check identifies an overrun error, bit OER is set to 1. Bit RDRF remains set to 1. If bit RIE is set to 1 in SCR3, an ERI interrupt is requested. See table 10.15 for the conditions for detecting an overrun error, and receive data processing. Note: No further receive operations are possible while a receive error flag is set. Bits OER, FER, PER, and RDRF must therefore be cleared to 0 before resuming reception. Figure 10.19 shows an example of the operation when receiving in synchronous mode.
Serial clock Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
1 frame RDRF OER LSI operation User processing RXI request RDRE cleared to 0 RDR data read RXI request
1 frame
ERI request in response to overrun error RDR data has not been read (RDRF = 1) Overrun error processing
Figure 10.19 Example of Operation when Receiving in Synchronous Mode
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Section 10 Serial Communication Interface
Simultaneous Transmit/Receive: Figure 10.20 shows an example of a flowchart for a simultaneous transmit/receive operation. This procedure should be followed for simultaneous transmission/reception after initializing SCI3.
Start
1
Read bit TDRE in SSR
TDRE = 1? Yes Write transmit data to TDR
No
1. Read the serial status register (SSR) and check that bit TDRE is set to 1, then write transmit data to the transmit data register (TDR). When data is written to TDR, bit TDRE is cleared to 0 automatically. 2. Read SSR and check that bit RDRF is set to 1. If it is, read the receive data in RDR. When the RDR data is read, bit RDRF is cleared to 0 automatically. 3. When continuing data transmission/reception, finish reading of bit RDRF and RDR before receiving the MSB (bit 7) of the current frame. Before transmitting the MSB (bit 7) of the current frame, also read TDRE = 1 to confirm that a write can be performed, then write data to TDR. When data is written to TDR, bit TDRE is cleared to 0 automatically, and when the data in RDR is read, bit RDRF is cleared to 0 automatically. 4. If an overrun error has occurred, read bit OER in SSR, and after carrying out the necessary error processing, clear bit OER to 0. Transmission and reception cannot be resumed if bit OER is set to 1. See figure 10.18 for details on overrun error processing.
Read bit OER in SSR
OER = 1? No Read bit RDRF in SSR
Yes
2
RDRF = 1? Yes Read receive data in RDR
No
4
Overrun error processing
3
Continue data transmission/reception? No Clear bits TE and RE to 0 in SCR
Yes
End
Figure 10.20 Example of Simultaneous Data Transmission/Reception Flowchart (Synchronous Mode)
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Section 10 Serial Communication Interface
Notes: 1. When switching from transmission to simultaneous transmission/reception, check that SCI3 has finished transmitting and that bits TDRE and TEND are set to 1, clear bit TE to 0, and then set bits TE and RE to 1 simultaneously with a single instruction. 2. When switching from reception to simultaneous transmission/reception, check that SCI3 has finished receiving, clear bit RE to 0, then check that bit RDRF and the error flags (OER, FER, and PER) are cleared to 0, and finally set bits TE and RE to 1 simultaneously with a single instruction. 10.3.6 Multiprocessor Communication Function
The multiprocessor communication function enables data to be exchanged among a number of processors on a shared communication line. Serial data communication is performed in asynchronous mode using the multiprocessor format (in which a multiprocessor bit is added to the transfer data). In multiprocessor communication, each receiver is assigned its own ID code. The serial communication cycle consists of two cycles, an ID transmission cycle in which the receiver is specified, and a data transmission cycle in which the transfer data is sent to the specified receiver. These two cycles are differentiated by means of the multiprocessor bit, 1 indicating an ID transmission cycle, and 0, a data transmission cycle. The sender first sends transfer data with a 1 multiprocessor bit added to the ID code of the receiver it wants to communicate with, and then sends transfer data with a 0 multiprocessor bit added to the transmit data. When a receiver receives transfer data with the multiprocessor bit set to 1, it compares the ID code with its own ID code, and if they are the same, receives the transfer data sent next. If the ID codes do not match, it skips the transfer data until data with the multiprocessor bit set to 1 is sent again. In this way, a number of processors can exchange data among themselves. Figure 10.21 shows an example of communication between processors using the multiprocessor format.
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Section 10 Serial Communication Interface
Sender Communication line
Receiver A (ID = 01)
Receiver B (ID = 02)
Receiver C (ID = 03)
Receiver D (ID = 04)
Serial data
H'01 (MPB = 1) ID transmission cycle (specifying the receiver)
H'AA (MPB = 0) Data transmission cycle (sending data to the receiver specified buy the ID) MPB: Multiprocessor bit
Figure 10.21 Example of Inter-Processor Communication Using Multiprocessor Format (Sending Data H'AA to Receiver A) There is a choice of four data transfer formats. If a multiprocessor format is specified, the parity bit specification is invalid. See table 10.14 for details. For details on the clock used in multiprocessor communication, see section 10.3.4, Operation in Asynchronous Mode. Multiprocessor Transmitting: Figure 10.22 shows an example of a flowchart for multiprocessor data transmission. This procedure should be followed for multiprocessor data transmission after initializing SCI3.
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Start
1
Read bit TDRE in SSR
TDRE = 1? Yes Set bit MPBT in SSR
No
1. Read the serial status register (SSR) and check that bit TDRE is set to 1, then set bit MPBT in SSR to 0 or 1 and write transmit data to the transmit data register (TDR). When data is written to TDR, bit TDRE is cleared to 0 automatically. 2. When continuing data transmission, be sure to read TDRE = 1 to confirm that a write can be performed before writing data to TDR. When data is written to TDR, bit TDRE is cleared to 0 automatically. 3. If a break is to be output when data transmission ends, set the port PCR to 1 and clear the port PDR to 0, then clear bit TE in SCR3 to 0.
Write transmit data to TDR
2
Continue data transmission? No Read bit TEND in SSR
Yes
TEND = 1? Yes
No
3
Break output? Yes Set PDR = 0, PCR = 1
No
Clear bit TE to 0 in SCR3
End
Figure 10.22 Example of Multiprocessor Data Transmission Flowchart
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Section 10 Serial Communication Interface
SCI3 operates as follows when transmitting data. SCI3 monitors bit TDRE in SSR, and when it is cleared to 0, recognizes that data has been written to TDR and transfers data from TDR to TSR. It then sets bit TDRE to 1 and starts transmitting. If bit TIE in SCR3 is set to 1 at this time, a TXI request is made. Serial data is transmitted from the TXD pin using the relevant data transfer format in table 10.14. When the stop bit is sent, SCI3 checks bit TDRE. If bit TDRE is cleared to 0, SCI3 transfers data from TDR to TSR, and when the stop bit has been sent, starts transmission of the next frame. If bit TDRE is set to 1, bit TEND in SSR is set to 1, and the mark state, in which 1s are transmitted, is established after the stop bit has been sent. If bit TEIE in SCR3 is set to 1 at this time, a TEI request is made. Figure 10.23 shows an example of the operation when transmitting using the multiprocessor format.
Start bit Serial data 1 0 D0 D1 1 frame Transmit data D7 Stop Start bit bit 1 0 D0 Transmit data D1 1 frame D7 Stop bit 1 Mark state 1
MPB 0/1
MPB 0/1
TDRE TEND LSI TXI request operation User processing TDRE cleared to 0 Data written to TDR TXI request TEI request
Figure 10.23 Example of Operation when Transmitting using Multiprocessor Format (8-Bit Data, Multiprocessor Bit, 1 Stop Bit) Multiprocessor Receiving: Figure 10.24 shows an example of a flowchart for multiprocessor data reception. This procedure should be followed for multiprocessor data reception after initializing SCI3.
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Start 1. Set bit MPIE to 1 in SCR3. 2. Read bits OER and FER in the serial status register (SSR) to determine if there is an error. If a receive error has occurred, execute receive error processing. 3. Read SSR and check that bit RDRF is set to 1. If it is, read the receive data in RDR and compare it with this receiver's own ID. If the ID is not this receiver's, set bit MPIE to 1 again. When the RDR data is read, bit RDRF is cleared to 0 automatically. 4. Read SSR and check that bit RDRF is set to 1, then read the data in RDR. 5. If a receive error has occurred, read bits OER and FER in SSR to identify the error, and after carrying out the necessary error processing, ensure that bits OER and FER are both cleared to 0. Reception cannot be resumed if either of these bits is set to 1. In the case of a framing error, a break can be detected by reading the value of the RXD pin.
1
Set bit MPIE to 1 in SCR3
2
Read bits OER and FER in SSR Yes
OER + FER = 1? No 3 Read bit RDRF in SSR
RDRF = 1? Yes Read receive data in RDR
No
Own ID? Yes Read bits OER and FER in SSR
No
OER + FER = 1? No 4 Read bit RDRF in SSR
Yes
RDRF = 1? Yes Read receive 4 data in RDR
No
5
Receive error processing
Continue data reception? No Clear bit RE to 0 in SCR3 End
Yes
(A)
Figure 10.24 Example of Multiprocessor Data Reception Flowchart
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Section 10 Serial Communication Interface
Start receive error processing Overrun error processing OER = 1? No FER = 1? No Clear bits OER and FER to 0 in SSR Yes Yes Yes Break? No Framing error processing
End of receive error processing
(A)
Figure 10.24 Example of Multiprocessor Data Reception Flowchart (cont) Figure 10.25 shows an example of the operation when receiving using the multiprocessor format.
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Start bit Serial data 1 0 D0 Receive data (ID1) D1 1 frame D7 Stop Start bit bit 1 0 D0 Receive data (Data1) D1 1 frame D7 Stop bit 1 Mark state (idle state) 1
MPB 1
MPB 0
MPIE
RDRF RDR value LSI operation User processing RXI request MPIE cleared to 0 RDRF cleared to 0 RDR data read When data is not this receiver's ID, MPIE is set to 1 again ID1
No RXI request RDR retains previous state
(a) When data does not match this receiver's ID
Start bit Serial data 1 0 D0
Receive data (ID2) D1 1 frame D7
MPB 1
Stop Start bit bit 1 0 D0
Receive data (Data2) D1 1 frame D7
MPB 0
Stop bit 1
Mark state (idle state) 1
MPIE
RDRF RDR value LSI operation User processing ID1 ID2 Data2
RXI request MPIE cleared to 0
RDRF cleared to 0 RDR data read
RXI request
RDRF cleared to 0 RDR data read MPIE set to 1 again
When data is this receiver's ID, reception is continued
(b) When data matches this receiver's ID
Figure 10.25 Example of Operation when Receiving using Multiprocessor Format (8-Bit Data, Multiprocessor Bit, 1 Stop Bit)
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Section 10 Serial Communication Interface
10.3.7
Interrupts
SCI3 can generate six kinds of interrupts: transmit end, transmit data empty, receive data full, and three receive error interrupts (overrun error, framing error, and parity error). These interrupts have the same vector address. The various interrupt requests are shown in table 10.16. Table 10.16 SCI3 Interrupt Requests
Interrupt Abbreviation RXI TXI TEI ERI Interrupt Request Interrupt request initiated by receive data full flag (RDRF) Interrupt request initiated by transmit data empty flag (TDRE) Interrupt request initiated by transmit end flag (TEND) Interrupt request initiated by receive error flag (OER, FER, PER) Vector Address H'002A
Each interrupt request can be enabled or disabled by means of bits TIE and RIE in SCR3. When bit TDRE is set to 1 in SSR, a TXI interrupt is requested. When bit TEND is set to 1 in SSR, a TEI interrupt is requested. These two interrupts are generated during transmission. The initial value of bit TDRE in SSR is 1. Therefore, if the transmit data empty interrupt request (TXI) is enabled by setting bit TIE to 1 in SCR3 before transmit data is transferred to TDR, a TXI interrupt will be requested even if the transmit data is not ready. Also, the initial value of bit TEND in SSR is 1. Therefore, if the transmit end interrupt request (TEI) is enabled by setting bit TEIE to 1 in SCR3 before transmit data is transferred to TDR, a TEI interrupt will be requested even if the transmit data has not been sent. Effective use of these interrupt requests can be made by having processing that transfers transmit data to TDR carried out in the interrupt service routine. To prevent the generation of these interrupt requests (TXI and TEI), on the other hand, the enable bits for these interrupt requests (bits TIE and TEIE) should be set to 1 after transmit data has been transferred to TDR. When bit RDRF is set to 1 in SSR, an RXI interrupt is requested, and if any of bits OER, PER, and FER is set to 1, an ERI interrupt is requested. These two interrupt requests are generated during reception.
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For further details, see section 3.3, Interrupts. 10.3.8 Application Notes
The following points should be noted when using SCI3. 1. Relation between writes to TDR and bit TDRE Bit TDRE in the serial status register (SSR) is a status flag that indicates that data for serial transmission has not been prepared in TDR. When data is written to TDR, bit TDRE is cleared to 0 automatically. When SCI3 transfers data from TDR to TSR, bit TDRE is set to 1. Data can be written to TDR irrespective of the state of bit TDRE, but if new data is written to TDR while bit TDRE is cleared to 0, the data previously stored in TDR will be lost of it has not yet been transferred to TSR. Accordingly, to ensure that serial transmission is performed dependably, you should first check that bit TDRE is set to 1, then write the transmit data to TDR once only (not two or more times). 2. Operation when a number of receive errors occur simultaneously If a number of receive errors are detected simultaneously, the status flags in SSR will be set to the states shown in table 10.17. If an overrun error is detected, data transfer from RSR to RDR will not be performed, and the receive data will be lost. Table 10.17 SSR Status Flag States and Receive Data Transfer
SSR Status Flags RDRF* OER 1 0 0 1 1 0 1 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 Receive Data Transfer (RSR RDR) Receive Error Status x O O x x O x Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error
Legend: O: Receive data is transferred from RSR to RDR. x : Receive data is not transferred from RSR to RDR. Note: * Bit RDRF retains its state prior to data reception.
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Section 10 Serial Communication Interface
3. Break detection and processing When a framing error is detected, a break can be detected by reading the value of the RXD pin directly. In a break, the input from the RXD pin becomes all 0s, with the result that bit FER is set and bit PER may also be set. SCI3 continues the receive operation even after receiving a break. Note, therefore, that even though bit FER is cleared to 0 it will be set to 1 again. 4. Mark state and break detection When bit TE is cleared to 0, the TXD pin functions as an I/O port whose input/output direction and level are determined by PDR and PCR. This fact can be used to set the TXD pin to the mark state, or to detect a break during transmission. To keep the communication line in the mark state (1 state) until bit TE is set to 1, set PCR = 1 and PDR = 1. Since bit TE is cleared to 0 at this time, the TXD pin functions as an I/O port and 1 is output. To detect a break during transmission, clear bit TE to 0 after setting PCR = 1 and PDR = 0. When bit TE is cleared to 0, the transmission unit is initialized regardless of the current transmission state, the TXD pin functions as an I/O port, and 0 is output from the TXD pin. 5. Receive error flags and transmit operation (synchronous mode only) When a receive error flag (OER, PER, or FER) is set to 1, transmission cannot be started even if bit TDRE is cleared to 0. The receive error flags must be cleared to 0 before starting transmission. Note also that receive error flags cannot be cleared to 0 even if bit RE is cleared to 0. 6. Receive data sampling timing and receive margin in asynchronous mode In asynchronous mode, SCI3 operates on a basic clock with a frequency 16 times the transfer rate. When receiving, SCI3 performs internal synchronization by sampling the falling edge of the start bit with the basic clock. Receive data is latched internally at the 8th rising edge of the basic clock. This is illustrated in figure 10.26.
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Section 10 Serial Communication Interface
16 clock pulses 8 clock pulses
0 7 15 0 7 15 0
Internal basic clock Receive data (RXD) Synchronization sampling timing
Start bit
D0
D1
Data sampling timing
Figure 10.26 Receive Data Sampling Timing in Asynchronous Mode Consequently, the receive margin in asynchronous mode can be expressed as shown in equation (1).
1 D - 0.5 M = (0.5 - )- - (L - 0.5) F x 100 . . . . . . . . . . . . . . . Equation (1) 2N N
where M: Receive margin (%) N: Ratio of bit rate to clock (N = 16) D: Clock duty (D = 0.5 to 1.0) L: Frame length (L = 9 to 12) F: Absolute value of clock frequency deviation Substituting 0 for F (absolute value of clock frequency deviation) and 0.5 for D (clock duty) in equation (1), a receive margin of 46.875% is given by equation (2). When D = 0.5 and F = 0,
M = {0.5 - 1/(2 x 16)} x 100 [%] = 46.875% . . . . . . . . . . . . . . . . . . Equation (2)
However, this is only a computed value, and a margin of 20% to 30% should be allowed when carrying out system design.
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Section 10 Serial Communication Interface
7. Relation between RDR reads and bit RDRF In a receive operation, SCI3 continually checks the RDRF flag. If bit RDRF is cleared to 0 when reception of one frame ends, normal data reception is completed. If bit RDRF is set to 1, this indicates that an overrun error has occurred. When the contents of RDR are read, bit RDRF is cleared to 0 automatically. Therefore, if bit RDR is read more than once, the second and subsequent read operations will be performed while bit RDRF is cleared to 0. Note that, when an RDR read is performed while bit RDRF is cleared to 0, if the read operation coincides with completion of reception of a frame, the next frame of data may be read. This is illustrated in figure 10.27.
Frame 1 Frame 2 Frame 3
Communication line
Data 1
Data 2
Data 3
RDRF
RDR
Data 1
Data 3
(A) RDR read
(B)
RDR read Data 1 is read at point (A) Data 2 is read at point (B)
Figure 10.27 Relation between RDR Read Timing and Data In this case, only a single RDR read operation (not two or more) should be performed after first checking that bit RDRF is set to 1. If two or more reads are performed, the data read the first time should be transferred to RAM, etc., and the RAM contents used. Also, ensure that there is sufficient margin in an RDR read operation before reception of the next frame is completed. To be precise in terms of timing, the RDR read should be completed before bit 7 is transferred in synchronous mode, or before the STOP bit is transferred in asynchronous mode.
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Section 11 14-Bit PWM
Section 11 14-Bit PWM
11.1 Overview
The H8/3644 Group is provided with a 14-bit PWM (pulse width modulator) on-chip, which can be used as a D/A converter by connecting a low-pass filter. 11.1.1 Features
Features of the 14-bit PWM are as follows. * Choice of two conversion periods A conversion period of 32,768/, with a minimum modulation width of 2/ or a conversion period of 16,384/, with a minimum modulation width of 1/ can be chosen. * Pulse division method for less ripple 11.1.2 Block Diagram
Figure 11.1 shows a block diagram of the 14-bit PWM.
PWDRL
/2 /4
PWM waveform generator PWCR
PWM Legend: PWDRL: PWM data register L PWDRU: PWM data register U PWCR: PWM control register
Figure 11.1 Block Diagram of the 14-Bit PWM
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Internal data bus
PWDRU
Section 11 14-Bit PWM
11.1.3
Pin Configuration
Table 11.1 shows the output pin assigned to the 14-bit PWM. Table 11.1 Pin Configuration
Name PWM output pin Abbrev. PWM I/O Output Function Pulse-division PWM waveform output
11.1.4
Register Configuration
Table 11.2 shows the register configuration of the 14-bit PWM. Table 11.2 Register Configuration
Name PWM control register PWM data register U PWM data register L Abbrev. PWCR PWDRU PWDRL R/W W W W Initial Value H'FE H'C0 H'00 Address H'FFD0 H'FFD1 H'FFD2
11.2
11.2.1
Bit
Register Descriptions
PWM Control Register (PWCR)
7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 PWCR0 0 W
Initial value Read/Write
PWCR is an 8-bit write-only register for input clock selection. Upon reset, PWCR is initialized to H'FE. Bits 7 to 1Reserved Bits: Bits 7 to 1 are reserved; they are always read as 1, and cannot be modified.
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Section 11 14-Bit PWM
Bit 0Clock Select 0 (PWCR0): Bit 0 selects the clock supplied to the 14-bit PWM. This bit is a write-only bit; it is always read as 1.
Bit 0: PWCR0 0 1 Note: * Description The input clock is /2 (t* = 2/). The conversion period is 16,384/, with a minimum modulation width of 1/ (initial value) The input clock is /4 (t* = 4/). The conversion period is 32,768/, with a minimum modulation width of 2/. t Period of PWM input clock
11.2.2 PWDRU
Bit
PWM Data Registers U and L (PWDRU, PWDRL)
7 1
6 1
5 0 W
4 0 W
3 0 W
2 0 W
1 0 W
0 0 W
PWDRU5 PWDRU4 PWDRU3 PWDRU2 PWDRU1 PWDRU0
Initial value Read/Write
PWDRL
Bit Initial value Read/Write 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W
PWDRL7 PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0
PWDRU and PWDRL form a 14-bit write-only register, with the upper 6 bits assigned to PWDRU and the lower 8 bits to PWDRL. The value written to PWDRU and PWDRL gives the total highlevel width of one PWM waveform cycle. When 14-bit data is written to PWDRU and PWDRL, the register contents are latched in the PWM waveform generator, updating the PWM waveform generation data. The 14-bit data should always be written in the following sequence: 1. Write the lower 8 bits to PWDRL. 2. Write the upper 6 bits to PWDRU.
PWDRU and PWDRL are write-only registers. If they are read, all bits are read as 1.
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Section 11 14-Bit PWM
Upon reset, PWDRU and PWDRL are initialized to H'C000.
11.3
Operation
When using the 14-bit PWM, set the registers in the following sequence. 1. Set bit PWM in port mode register 1 (PMR1) to 1 so that pin P14/PWM is designated for PWM output. 2. Set bit PWCR0 in the PWM control register (PWCR) to select a conversion period of either 32,768/ (PWCR0 = 1) or 16,384/ (PWCR0 = 0). 3. Set the output waveform data in PWM data registers U and L (PWDRU/L). Be sure to write in the correct sequence, first PWDRL then PWDRU. When data is written to PWDRU, the data in these registers will be latched in the PWM waveform generator, updating the PWM waveform generation in synchronization with internal signals. One conversion period consists of 64 pulses, as shown in figure 11.2. The total of the highlevel pulse widths during this period (TH) corresponds to the data in PWDRU and PWDRL. This relation can be represented as follows.
TH = (data value in PWDRU and PWDRL + 64) x t/2
where t is the PWM input clock period, either 2/ (bit PWCR0 = 0) or 4/ (bit PWCR0 = 1). Example: Settings in order to obtain a conversion period of 8,192 s: When bit PWCR0 = 0, the conversion period is 16,384/, so must be 2 MHz. In this case tfn = 128 s, with 1/ (resolution) = 0.5 s. When bit PWCR0 = 1, the conversion period is 32,768/, so must be 4 MHz. In this case tfn = 128 s, with 2/ (resolution) = 0.5 s. Accordingly, for a conversion period of 8,192 s, the system clock frequency () must be 2 MHz or 4 MHz.
1 conversion period t f1 t f2 t f63 t f64
t H1
t H2
t H3
t H63
t H64
TH = t H1 + t H2 + t H3 + ..... t H64 t f1 = t f2 = t f3 ..... = t f64
Figure 11.2 PWM Output Waveform
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Section 12 A/D Converter
Section 12 A/D Converter
12.1 Overview
The H8/3644 Group includes on-chip a resistance-ladder-based successive-approximation analogto-digital converter, and can convert up to 8 channels of analog input. 12.1.1 Features
The A/D converter has the following features. * 8-bit resolution * Eight input channels * Conversion time: approx. 12.4 s per channel (at 5-MHz operation) * Built-in sample-and-hold function * Interrupt requested on completion of A/D conversion * A/D conversion can be started by external trigger input
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Section 12 A/D Converter
12.1.2
Block Diagram
Figure 12.1 shows a block diagram of the A/D converter.
ADTRG AMR AN 0 AN 1 AN 2 AN 3 AN 4 AN 5 AN 6 AN 7
AVCC + Comparator -
Control logic
AVCC Reference voltage AVSS
AVSS ADRR
Legend: AMR: A/D mode register ADSR: A/D start register ADRR: A/D result register
Figure 12.1 Block Diagram of the A/D Converter
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Internal data bus
Multiplexer
ADSR
IRRAD
Section 12 A/D Converter
12.1.3
Pin Configuration
Table 12.1 shows the A/D converter pin configuration. Table 12.1 Pin Configuration
Name Analog power supply Analog ground Analog input 0 Analog input 1 Analog input 2 Analog input 3 Analog input 4 Analog input 5 Analog input 6 Analog input 7 External trigger input Abbrev. AVCC AVSS AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ADTRG I/O Input Input Input Input Input Input Input Input Input Input Input Function Power supply and reference voltage of analog part Ground and reference voltage of analog part Analog input channel 0 Analog input channel 1 Analog input channel 2 Analog input channel 3 Analog input channel 4 Analog input channel 5 Analog input channel 6 Analog input channel 7 External trigger input for starting A/D conversion
12.1.4
Register Configuration
Table 12.2 shows the A/D converter register configuration. Table 12.2 Register Configuration
Name A/D mode register A/D start register A/D result register Abbrev. AMR ADSR ADRR R/W R/W R/W R Initial Value H'30 H'7F Undefined Address H'FFC4 H'FFC6 H'FFC5
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Section 12 A/D Converter
12.2
12.2.1
Bit
Register Descriptions
A/D Result Register (ADRR)
7 ADR7 6 ADR6 R 5 ADR5 R 4 ADR4 R 3 ADR3 R 2 ADR2 R 1 ADR1 R 0 ADR0 R
Initial value Read/Write
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
R
The A/D result register (ADRR) is an 8-bit read-only register for holding the results of analog-todigital conversion. ADRR can be read by the CPU at any time, but the ADRR values during A/D conversion are undefined. After A/D conversion is complete, the conversion result is stored in ADRR as 8-bit data; this data is held in ADRR until the next conversion operation starts. ADRR is not cleared on reset. 12.2.2
Bit Initial value Read/Write
A/D Mode Register (AMR)
7 CKS 0 R/W 6 TRGE 0 R/W 5 1 4 1 3 CH3 0 R/W 2 CH2 0 R/W 1 CH1 0 R/W 0 CH0 0 R/W
AMR is an 8-bit read/write register for specifying the A/D conversion speed, external trigger option, and the analog input pins. Upon reset, AMR is initialized to H'30.
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Section 12 A/D Converter
Bit 7Clock Select (CKS): Bit 7 sets the A/D conversion speed.
Conversion Time Bit 7: CKS 0 1 Conversion Period 62/ (initial value) 31/ = 2 MHz 31 s 15.5 s = 5 MHz 12.4 s 2 * = 8 MHz* 7.75 s
1
Notes: 1. Applies only to F-ZTAT, R of the ZTAT, and R of the mask ROM version. 2. Operation is not guaranteed if the conversion time is less than 12.4 s. Set bit 7 for a value of at least 12.4 s.
Bit 6External Trigger Select (TRGE): Bit 6 enables or disables the start of A/D conversion by external trigger input.
Bit 6: TRGE 0 1 Note: * Description Disables start of A/D conversion by external trigger (initial value) Enables start of A/D conversion by rising or falling edge of external trigger at pin ADTRG* The external trigger (ADTRG) edge is selected by bit INTEG5 of IEGR2. See section 3.3.2, Interrupt Edge Select Register 2 (IEGR2) for details.
Bits 5 and 4Reserved Bits: Bits 5 and 4 are reserved; they are always read as 1, and cannot be modified.
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Section 12 A/D Converter
Bits 3 to 0Channel Select (CH3 to CH0): Bits 3 to 0 select the analog input channel. The channel selection should be made while bit ADSF is cleared to 0.
Bit 3: CH3 0 Bit 2: CH2 0 1 Bit 1: CH1 * 0 1 1 0 0 1 1 0 1 Legend: * Don't care Bit 0: CH0 * 0 1 0 1 0 1 0 1 0 1 0 1 Analog Input Channel No channel selected AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Reserved Reserved Reserved Reserved (initial value)
12.2.3
Bit
A/D Start Register (ADSR)
7 ADSF 0 R/W 6 1 5 1 4 1 3 1 2 1 1 1 0 1
Initial value Read/Write
The A/D start register (ADSR) is an 8-bit read/write register for starting and stopping A/D conversion. A/D conversion is started by writing 1 to the A/D start flag (ADSF) or by input of the designated edge of the external trigger signal, which also sets ADSF to 1. When conversion is complete, the converted data is set in the A/D result register (ADRR), and at the same time ADSF is cleared to 0.
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Section 12 A/D Converter
Bit 7A/D Start Flag (ADSF): Bit 7 controls and indicates the start and end of A/D conversion.
Bit 7: ADSF 0 1 Description Read: Indicates the completion of A/D conversion Write: Stops A/D conversion Read: Indicates A/D conversion in progress Write: Starts A/D conversion (initial value)
Bits 6 to 0Reserved Bits: Bits 6 to 0 are reserved; they are always read as 1, and cannot be modified.
12.3
12.3.1
Operation
A/D Conversion Operation
The A/D converter operates by successive approximations, and yields its conversion result as 8-bit data. A/D conversion begins when software sets the A/D start flag (bit ADSF) to 1. Bit ADSF keeps a value of 1 during A/D conversion, and is cleared to 0 automatically when conversion is complete. The completion of conversion also sets bit IRRAD in interrupt request register 2 (IRR2) to 1. An A/D conversion end interrupt is requested if bit IENAD in interrupt enable register 2 (IENR2) is set to 1. If the conversion time or input channel needs to be changed in the A/D mode register (AMR) during A/D conversion, bit ADSF should first be cleared to 0, stopping the conversion operation, in order to avoid malfunction. 12.3.2 Start of A/D Conversion by External Trigger Input
The A/D converter can be made to start A/D conversion by input of an external trigger signal. External trigger input is enabled at pin ADTRG when bit TRGE in AMR is set to 1. Then when the input signal edge designated in bit INTEG5 of interrupt edge select register 2 (IEGR2) is detected at pin ADTRG, bit ADSF in ADSR will be set to 1, starting A/D conversion. Figure 12.2 shows the timing.
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Section 12 A/D Converter
Pin ADTRG (when bit INTEG5 = 0) ADSF A/D conversion
Figure 12.2 External Trigger Input Timing
12.4
Interrupts
When A/D conversion ends (ADSF changes from 1 to 0), bit IRRAD in interrupt request register 2 (IRR2) is set to 1. A/D conversion end interrupts can be enabled or disabled by means of bit IENAD in interrupt enable register 2 (IENR2). For further details see section 3.3, Interrupts.
12.5
Typical Use
An example of how the A/D converter can be used is given below, using channel 1 (pin AN1) as the analog input channel. Figure 12.3 shows the operation timing. 1. Bits CH3 to CH0 of the A/D mode register (AMR) are set to 0101, making pin AN1 the analog input channel. A/D interrupts are enabled by setting bit IENAD to 1, and A/D conversion is started by setting bit ADSF to 1. 2. When A/D conversion is complete, bit IRRAD is set to 1, and the A/D conversion result is stored in the A/D result register (ADRR). At the same time ADSF is cleared to 0, and the A/D converter goes to the idle state. 3. Bit IENAD = 1, so an A/D conversion end interrupt is requested. 4. The A/D interrupt handling routine starts. 5. The A/D conversion result is read and processed. 6. The A/D interrupt handling routine ends. If ADSF is set to 1 again afterward, A/D conversion starts and steps 2 through 6 take place. Figures 12.4 and 12.5 show flow charts of procedures for using the A/D converter.
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Interrupt (IRRAD) Set *
IENAD
ADSF
A/D conversion starts
Set *
Set *
Channel 1 (AN 1) operation state Idle A/D conversion (1) Idle
A/D conversion (2)
Idle
Read conversion result A/D conversion result (1)
Read conversion result A/D conversion result (2) Conversion result is reset when next conversion starts
ADRR
Figure 12.3 Typical A/D Converter Operation Timing
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Note: * ( ) indicates instruction execution by software.
Section 12 A/D Converter
Section 12 A/D Converter
Start
Set A/D conversion speed and input channel
Disable A/D conversion end interrupt
Start A/D conversion
Read ADSR
No ADSF = 0? Yes Read ADRR data
Yes
Perform A/D conversion? No End
Figure 12.4 Flow Chart of Procedure for Using A/D Converter (1) (Polling by Software)
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Section 12 A/D Converter
Start
Set A/D conversion speed and input channels
Enable A/D conversion end interrupt
Start A/D conversion
A/D conversion end interrupt? No
Yes
Clear bit IRRAD to 0 in IRR2
Read ADRR data
Yes
Perform A/D conversion? No End
Figure 12.5 Flow Chart of Procedure for Using A/D Converter (2) (Interrupts Used)
12.6
Application Notes
* Data in the A/D result register (ADRR) should be read only when the A/D start flag (ADSF) in the A/D start register (ADSR) is cleared to 0. * Changing the digital input signal at an adjacent pin during A/D conversion may adversely affect conversion accuracy.
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Section 12 A/D Converter
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Section 13 Electrical Characteristics
Section 13 Electrical Characteristics
13.1 Absolute Maximum Ratings
Table 13.1 lists the absolute maximum ratings. Table 13.1 Absolute Maximum Ratings*1
Item Power supply voltage Analog power supply voltage Programming voltage Input voltage HD6473644 Symbol VCC AVCC VPP Value -0.3 to +7.0 -0.3 to +7.0 -0.3 to +13.0 -0.3 to +13.0 -0.3 to VCC +0.3 -0.3 to +13.0 Topr Tstg -20 to +75 -55 to +125 Unit V V V V V V C C 2 2 Note
HD64F3644, HD64F3643, FVPP HD64F3642A Ports other than Port B Port B TEST (HD64F3644, HD64F3643,HD64F3642A) Vin
-0.3 to AVCC +0.3 V
Operating temperature Storage temperature
Notes: 1. Permanent damage may occur to the chip if maximum ratings are exceeded. Normal operation should be under the conditions specified in Electrical Characteristics. Exceeding these values can result in incorrect operation and reduced reliability. 2. The voltage at the FVPP and TEST pins should not exceed 13 V, including peak overshoot.
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Section 13 Electrical Characteristics
13.2
13.2.1
Electrical Characteristics (ZTATTM, Mask ROM Version)
Power Supply Voltage and Operating Range
The power supply voltage and operating range are indicated by the shaded region in the figures below. 1. Power supply voltage vs. oscillator frequency range
10.0
32.768
f OSC (MHz)
5.0
2.0
2.7*1
fw (kHz)
4.0
5.5 VCC (V)
2.7*1
4.0
5.5 VCC (V)
* Active mode (high speed) * Sleep mode (high speed)
* All operating modes
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Section 13 Electrical Characteristics
2. Power supply voltage vs. clock frequency range
5.0
16.384
SUB (kHz)
(MHz)
2.5
8.192 4.096
0.5 2.7 *1 4.0 5.5 VCC (V) 2.7 *1 4.0 5.5 VCC (V)
* Active (high speed) mode * Sleep (high speed) mode (except CPU)
* Subactive mode * Subsleep mode (except CPU) * Watch mode (except CPU)
625.00
(kHz)
39.0625
7.8125
2.7*1
4.0
5.5 VCC (V)
* Active (medium speed) mode * Sleep (medium speed) mode (except CPU)
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Section 13 Electrical Characteristics
3. Analog power supply voltage vs. A/D converter guaranteed accuracy range
5.0
(MHz)
2.5
Do not exceed the maximum conversion time value.
0.5 2.7*2 4.0 4.5 5.5 AVCC (V) * Active (medium speed) mode * Sleep (medium speed) mode
* Active (high speed) mode * Sleep (high speed) mode
Notes: 1. 2.5 V for the HD6433644, HD6433643, HD6433642, HD6433641 and HD6433640. 2. The voltage for guaranteed A/D conversion operation is 2.5 (V).
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Section 13 Electrical Characteristics
13.2.2
DC Characteristics (HD6473644)
Table 13.2 lists the DC characteristics of the HD6473644. Table 13.2 DC Characteristics VCC = 4.0 V to 5.5 V, VSS = 0.0 V, Ta = -20C to +75C unless otherwise indicated.
Applicable Symbol Pins Values Min Typ Max VCC +0.3 Unit Test Condition V Notes
Item
Input high VIH voltage
RES, 0.8 VCC INT0 to INT7, IRQ0 to IRQ3, ADTRG, TMIB, TMRIV, TMCIV, 0.9 VCC FTCI, FTIA, FTIB, FTIC, FTID, SCK1, SCK3, TRGV SI1, RXD, 0.7 VCC P10, P14 to P17, P20 to P22, P30 to P32, P50 to P57, 0.8 VCC P60 to P67, P73 to P77, P80 to P87, P90 to P94 PB0 to PB7 0.7 VCC 0.8 VCC
VCC +0.3
VCC = 2.7 V to 5.5 V including subactive mode V
VCC +0.3
VCC +0.3
VCC = 2.7 V to 5.5 V including subactive mode
AVCC +0.3 V AVCC +0.3 VCC = 2.7 V to 5.5 V including subactive mode V VCC = 2.7 V to 5.5 V including subactive mode
OSC1
VCC - 0.5 VCC - 0.3

VCC +0.3 VCC +0.3
Note: Connect the TEST pin to VSS.
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Section 13 Electrical Characteristics Applicable Symbol Pins VIL Values Min Typ Max 0.2 VCC Unit Test Condition Notes V
Item Input low voltage
RES, -0.3 INT0 to INT7, IRQ0 to IRQ3, ADTRG, TMIB, TMRIV, TMCIV, -0.3 FTCI, FTIA, FTIB, FTIC, FTID, SCK1, SCK3, TRGV -0.3 SI1, RXD, P10, P14 to P17, P20 to P22, P30 to P32, P50 to P57, P60 to P67, -0.3 P73 to P77, P80 to P87, P90 to P94, PB0 to PB7 OSC1 -0.3 -0.3
0.1 VCC
VCC = 2.7 V to 5.5 V including subactive mode V
0.3 VCC
0.2 VCC
VCC = 2.7 V to 5.5 V including subactive mode V VCC = 2.7 V to 5.5 V including subactive mode V -IOH = 1.5 mA

0.5 0.3
Output high voltage
VOH
P10, P14 to P17, P20 to P22, P30 to P32, P50 to P57, P60 to P67, P73 to P77, P80 to P87, P90 to P94
VCC - 1.0 VCC - 0.5

VCC = 2.7 V to 5.5 V -IOH = 0.1 mA
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Section 13 Electrical Characteristics Applicable Symbol Pins VOL Values Min Typ Max 0.6 Unit Test Condition Notes V IOL = 1.6 mA
Item Output low voltage
P10, P14 to P17, P20 to P22, P30 to P32, P50 to P57, P73 to P77, P80 to P87, P90 to P94 P60 to P67
0.4
VCC = 2.7 V to 5.5 V IOL = 0.4 mA V IOL = 10.0 mA IOL = 1.6 mA VCC = 2.7 V to 5.5 V IOL = 0.4 mA A Vin = 0.5 V to (VCC -0.5 V)

1.0 0.4 0.4
Input/ output leakage current
| IIL |
OSC1, P10, P14 to P17, P20 to P22, P30 to P32, P50 to P57, P60 to P67, P73 to P77, P80 to P87, P90 to P94 PB0 to PB7
1.0

1.0 20
A A
Vin = 0.5 V to (AVCC -0.5 V) Vin = 0.5 V to (VCC -0.5 V) VCC = 5 V, Vin = 0 V VCC = 2.7 V, Vin = 0 V Reference value
Input leakage current Pull-up MOS current Input capacitance
| IIL |
RES, IRQ0
-Ip
P10, P14 to P17, 50 P30 to P32, P50 to P57 All input pins except RES RES IRQ0
25
300 15.0 60.0 30.0
A
Cin
pF
f = 1 MHz, Vin = 0 V, Ta = 25C
Rev. 6.00 Sep 12, 2006 page 363 of 526 REJ09B0326-0600
Section 13 Electrical Characteristics Applicable Symbol Pins VCC Values Min Typ 10 Max 15 Unit Test Condition Notes mA Active (highspeed) mode VCC = 5 V, fOSC = 10 MHz VCC = 2.7 V, fOSC = 10 MHz mA Active (mediumspeed) mode VCC = 5 V, fOSC = 10 MHz VCC = 2.7 V, fOSC = 10 MHz mA Sleep (highspeed) mode VCC = 5 V, fOSC = 10 MHz VCC = 2.7 V, fOSC = 10 MHz mA 1, 2
Item
Active IOPE1 mode current dissipation
5
1, 2 Reference value 1, 2
IOPE2
VCC
2
3
1
1, 2 Reference value 1, 2
Sleep ISLEEP1 mode current dissipation
VCC
5
7
2
1, 2 Reference value
ISLEEP2
VCC
2
3
Sleep (medium- 1, 2 speed) mode VCC = 5 V, fOSC = 10 MHz VCC = 2.7 V, fOSC = 10 MHz 1, 2 Reference value 1, 2
1
Subactive ISUB mode current dissipation
VCC
10
20
A
VCC = 2.7 V 32-kHz crystal resonator (SUB = W /2) VCC = 2.7 V 32-kHz crystal resonator (SUB = W /8)
10
1, 2 Reference value
Rev. 6.00 Sep 12, 2006 page 364 of 526 REJ09B0326-0600
Section 13 Electrical Characteristics Applicable Symbol Pins VCC Values Min Typ 5 Max 10 Unit Test Condition Notes A VCC = 2.7 V 32-kHz crystal resonator (SUB = W /2) VCC = 2.7 V 32-kHz crystal resonator 32-kHz crystal resonator not used 1, 2
Item
Subsleep ISUBSP mode current dissipation Watch IWATCH mode current dissipation Standby ISTBY mode current dissipation RAM data VRAM retaining voltage
VCC
6
A
1, 2
VCC
5
A
1, 2
VCC
2
V
Notes: 1. Pin states during current measurement are given below. RES Pin Internal State Operates Operates (OSC/128) Only timers operate Only timers operate (OSC/128) VCC VCC VCC VCC Operates Only timers operate, CPU stops Only time base operates, CPU stops CPU and timers both stop VCC VCC VCC VCC System clock oscillator: ceramic or crystal Subclock oscillator: Pin X1 = VCC 2. Excludes current in pull-up MOS transistors and output buffers. Rev. 6.00 Sep 12, 2006 page 365 of 526 REJ09B0326-0600 System clock oscillator: ceramic or crystal Subclock oscillator: crystal VCC Other Pins VCC
Mode
Oscillator Pins System clock oscillator: ceramic or crystal Subclock oscillator: Pin X1 = VCC
Active (high-speed) VCC mode Active (mediumspeed) mode Sleep (high-speed) VCC mode Sleep (mediumspeed) mode Subactive mode Subsleep mode Watch mode Standby mode
Section 13 Electrical Characteristics Values Item Allowable output low current (per pin) Allowable output low current (total) Allowable output high current (per pin) Allowable output high current (total) Output pins except port 6 Port 6 Output pins except port 6 Port 6 All output pins All output pins -IOH (-IOH) IOL Symbol IOL Min Typ Max 2 10 40 80 2 30 mA mA mA Unit mA
Rev. 6.00 Sep 12, 2006 page 366 of 526 REJ09B0326-0600
Section 13 Electrical Characteristics
13.2.3
AC Characteristics (HD6473644)
Table 13.3 lists the control signal timing, and tables 13.4 and 13.5 list the serial interface timing of the HD6473644. Table 13.3 Control Signal Timing VCC = 4.0 V to 5.5 V, VSS = 0.0 V, Ta = -20C to +75C, unless otherwise specified.
Applicable Pins Values Min Typ Max 10 Unit MHz Test Condition VCC = 2.7 V to 5.5 V VCC = 2.7 V to 5.5 V *1 Figure 13.1 VCC = 2.7 V to 5.5 V *1 VCC = 2.7 V to 5.5 V VCC = 2.7 V to 5.5 V VCC = 2.7 V to 5.5 V *2 Reference Figure
Item System clock oscillation frequency OSC clock (OSC) cycle time System clock () cycle time Subclock oscillation frequency Watch clock (W ) cycle time Subclock (SUB) cycle time Instruction cycle time Oscillation stabilization time (crystal resonator) Oscillation stabilization time (ceramic resonator)
Symbol fOSC tOSC tcyc fW tW tsubcyc
OSC1, OSC2 2
OSC1, OSC2 100 2 X1, X2 X1, X2 2 2
1000 ns 128 25.6 tOSC s kHz s tW
32.768 30.5 8 40 60 20 40 2 15 15
tcyc VCC = 2.7 V to 5.5 V tsubcyc ms VCC = 2.7 V to 5.5 V ms VCC = 2.7 V to 5.5 V s ns ns ns ns tcyc VCC = 2.7 V to 5.5 V VCC = 2.7 V to 5.5 V Figure 13.1 VCC = 2.7 V to 5.5 V VCC = 2.7 V to 5.5 V VCC = 2.7 V to 5.5 V VCC = 2.7 V to 5.5 V Figure 13.2
trc
OSC1, OSC2
trc
OSC1, OSC2 X1, X2 OSC1 OSC1 40 40 RES 10
Oscillation stabilization trc time External clock high width External clock low width External clock rise time External clock fall time Pin RES low width tCPH tCPL tCPr tCPf tREL
Rev. 6.00 Sep 12, 2006 page 367 of 526 REJ09B0326-0600
Section 13 Electrical Characteristics
Applicable Symbol Pins tIH IRQ0 to IRQ3, INT0 to INT7, ADTRG, TMIB, TMCIV, TMRIV, FTCI, FTIA, FTIB, FTIC, FTID, TRGV IRQ0 to IRQ3, INT6, INT7, ADTRG, TMIB, TMCIV, TMRIV, FTCI, FTIA, FTIB, FTIC, FTID, TRGV Values Min 2 Typ Max Unit tcyc tsubcyc Test Condition Reference Figure Figure 13.3
Item Input pin high width
Input pin low width
tIL
2
tcyc VCC = 2.7 V to 5.5 V tsubcyc
Notes: 1. A frequency between 1 MHz to 10 MHz is required when an external clock is input. 2. Selected with SA1 and SA0 of system clock control register 2 (SYSCR2).
Rev. 6.00 Sep 12, 2006 page 368 of 526 REJ09B0326-0600
Section 13 Electrical Characteristics
Table 13.4 Serial Interface (SCI1) Timing VCC = 4.0 V to 5.5 V, VSS = 0.0 V, Ta = -20C to +75C, unless otherwise specified.
Applicable Symbol Pins tScyc tSCKH tSCKL tSCKr SCK1 SCK1 SCK1 SCK1 Values Min 2 0.4 0.4 tSCKf SCK1 SO1 SI1 180 360 tSIH SI1 180 360 Typ Max 60 80 60 80 200 350 ns VCC = 2.7 V to 5.5 V ns VCC = 2.7 V to 5.5 V ns VCC = 2.7 V to 5.5 V ns VCC = 2.7 V to 5.5 V Reference Unit Test Condition Figure tcyc tScyc tScyc ns VCC = 2.7 V to 5.5 V VCC = 2.7 V to 5.5 V VCC = 2.7 V to 5.5 V VCC = 2.7 V to 5.5 V Figure 13.4
Item Input serial clock cycle time Input serial clock high width Input serial clock low width Input serial clock rise time Input serial clock fall time
Serial output data tSOD delay time Serial input data setup time Serial input data hold time tSIS
Rev. 6.00 Sep 12, 2006 page 369 of 526 REJ09B0326-0600
Section 13 Electrical Characteristics
Table 13.5 Serial Interface (SCI3) Timing VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = 0.0 V, Ta = -20C to +75C, unless otherwise specified.
Values Item Input clock cycle Synchronous tSCKW tTXD Symbol Asynchronous tScyc Min 4 6 0.4 Receive data setup time (synchronous) Receive data hold time (synchronous) tRXS Typ Max 0.6 1 1 ns VCC = 4.0 V to 5.5 V ns VCC = 4.0 V to 5.5 V tScyc tcyc VCC = 4.0 V to 5.5 V Figure 13.6 Unit Test Condition tcyc Reference Figure Figure 13.5
Input clock pulse width Transmit data delay time (synchronous)
200.0 400.0
tRXH
200.0 400.0
Rev. 6.00 Sep 12, 2006 page 370 of 526 REJ09B0326-0600
Section 13 Electrical Characteristics
13.2.4
DC Characteristics (HD6433644, HD6433643, HD6433642, HD6433641, HD6433640)
Table 13.6 lists the DC characteristics of the HD6433644, the HD6433643, the HD6433642, the HD6433641 and the HD6433640. Table 13.6 DC Characteristics VCC = 4.0 V to 5.5 V, VSS = 0.0 V, Ta = -20C to +75C unless otherwise indicated.
Applicable Symbol Pins Values Min Typ Max VCC +0.3 Unit Test Condition V Notes
Item
Input high VIH voltage
RES, 0.8 VCC INT0 to INT7, IRQ0 to IRQ3, ADTRG, TMIB, TMRIV, TMCIV, 0.9 VCC FTCI, FTIA, FTIB, FTIC, FTID, SCK1, SCK3, TRGV SI1, RXD, 0.7 VCC P10, P14 to P17, P20 to P22, P30 to P32, P50 to P57, 0.8 VCC P60 to P67, P73 to P77, P80 to P87, P90 to P94 PB0 to PB7 0.7 VCC 0.8 VCC
VCC +0.3
VCC = 2.5 V to 5.5 V including subactive mode V
VCC +0.3
VCC +0.3
VCC = 2.5 V to 5.5 V including subactive mode

AVCC +0.3 V AVCC +0.3 VCC = 2.5 V to 5.5 V including subactive mode V VCC = 2.5 V to 5.5 V including subactive mode
OSC1
VCC -0.5 VCC -0.3
VCC +0.3 VCC +0.3
Note: Connect the TEST pin to VSS.
Rev. 6.00 Sep 12, 2006 page 371 of 526 REJ09B0326-0600
Section 13 Electrical Characteristics Applicable Symbol Pins Values Min Typ Max 0.2 VCC Unit Test Condition V Notes
Item
Input low VIL voltage
-0.3 RES, INT0 to INT7, IRQ0 to IRQ3, ADTRG, TMIB, TMRIV, TMCIV, FTCI, FTIA, -0.3 FTIB, FTIC, FTID, SCK1, SCK3, TRGV -0.3 SI1, RXD, P10, P14 to P17, P20 to P22, P30 to P32, P50 to P57, P60 to P67, -0.3 P73 to P77, P80 to P87, P90 to P94, PB0 to PB7 OSC1 -0.3 -0.3
0.1 VCC
VCC = 2.5 V to 5.5 V including subactive mode V
0.3 VCC
0.2 VCC
VCC = 2.5 V to 5.5 V including subactive mode V VCC = 2.5 V to 5.5 V including subactive mode

0.5 0.3
Rev. 6.00 Sep 12, 2006 page 372 of 526 REJ09B0326-0600
Section 13 Electrical Characteristics Applicable Symbol Pins VOH Values Min Typ Max Unit Test Condition Notes V -IOH = 1.5 mA
Item Output high voltage
P10, P14 to P17, VCC -1.0 P20 to P22, P30 to P32, P50 to P57, VCC -0.5 P60 to P67, P73 to P77, P80 to P87, P90 to P94 P10, P14 to P17, P20 to P22, P30 to P32, P50 to P57, P73 to P77, P80 to P87, P90 to P94 P60 to P67
VCC = 2.5 V to 5.5 V -IOH = 0.1 mA
Output low voltage
VOL
0.6
V
IOL = 1.6 mA
0.4
VCC = 2.5 V to 5.5 V IOL = 0.4 mA V IOL = 10.0 mA IOL = 1.6 mA VCC = 2.5 V to 5.5 V IOL = 0.4 mA A Vin = 0.5 V to (VCC -0.5 V)

1.0 0.4 0.4
Input/ output leakage current
| IIL |
OSC1, P10, P14 to P17, P20 to P22, P30 to P32, P50 to P57, P60 to P67, P73 to P77, P80 to P87, P90 to P94 PB0 to PB7
1.0

1.0 1
A A
Vin = 0.5 V to (AVCC -0.5 V) Vin = 0.5 V to (VCC -0.5 V) VCC = 5 V, Vin = 0 V VCC = 2.5 V, Vin = 0 V Reference value
Input leakage current Pull-up MOS current
| IIL |
RES, IRQ0
-Ip
P10, P14 to P17, 50 P30 to P32, P50 to P57
25
300
A
Rev. 6.00 Sep 12, 2006 page 373 of 526 REJ09B0326-0600
Section 13 Electrical Characteristics Applicable Symbol Pins Cin All input pins except RES RES IRQ0 Active IOPE1 mode current dissipation VCC Values Min Typ 10 Max 15.0 15.0 15.0 15 mA Active (highspeed) mode VCC = 5 V, fOSC = 10 MHz VCC = 2.5 V, fOSC = 10 MHz mA 1, 2 Unit pF Test Condition Notes f = 1 MHz, Vin = 0 V, Ta = 25C
Item Input capacitance
5
1, 2 Reference value
IOPE2
VCC
2
3
Active (medium- 1, 2 speed) mode VCC = 5 V, fOSC = 10 MHz VCC = 2.5 V, fOSC = 10 MHz 1, 2 Reference value 1, 2
1
Sleep ISLEEP1 mode current dissipation
VCC
5
7
mA
Sleep (highspeed) mode VCC = 5 V, fOSC = 10 MHz VCC = 2.5 V, fOSC = 10 MHz
2
1, 2 Reference value
ISLEEP2
VCC
2
3
mA
Sleep (medium- 1, 2 speed) mode VCC = 5 V, fOSC = 10 MHz VCC = 2.5 V, fOSC = 10 MHz 1, 2 Reference value 1, 2
1
Subactive ISUB mode current dissipation
VCC
10
20
A
VCC = 2.5 V 32-kHz crystal resonator (SUB = W /2) VCC = 2.5 V 32-kHz crystal resonator (SUB = W /8)
10
1, 2 Reference value
Rev. 6.00 Sep 12, 2006 page 374 of 526 REJ09B0326-0600
Section 13 Electrical Characteristics Applicable Symbol Pins VCC Values Min Typ 5 Max 10 Unit A Test Condition VCC = 2.5 V 32-kHz crystal resonator (SUB = W /2) VCC = 2.5 V 32-kHz crystal resonator 32-kHz crystal resonator not used Notes 1, 2
Item
Subsleep ISUBSP mode current dissipation Watch IWATCH mode current dissipation Standby ISTBY mode current dissipation RAM data VRAM retaining voltage
VCC
6
A
1, 2
VCC
5
A
1, 2
VCC
2
V
Notes: 1. Pin states during current measurement are given below. RES Pin Internal State VCC Operates Operates (OSC/128) VCC Only timers operate VCC Only timers operate (OSC/128) VCC VCC VCC VCC Operates VCC Only timers operate, VCC CPU stops Only time base VCC operates, CPU stops CPU and timers both stop VCC System clock oscillator: ceramic or crystal Subclock oscillator: crystal System clock oscillator: ceramic or crystal Subclock oscillator: Pin X1 = VCC 2. Excludes current in pull-up MOS transistors and output buffers. Rev. 6.00 Sep 12, 2006 page 375 of 526 REJ09B0326-0600 Other Pins VCC
Mode Active (high-speed) mode Active (mediumspeed) mode Sleep (high-speed) mode Sleep (mediumspeed) mode Subactive mode Subsleep mode Watch mode Standby mode
Oscillator Pins System clock oscillator: ceramic or crystal Subclock oscillator: Pin X1 = VCC
Section 13 Electrical Characteristics Values Item Allowable output low current (per pin) Allowable output low current (total) Allowable output high current (per pin) Allowable output high current (total) Output pins except port 6 Port 6 Output pins except port 6 Port 6 All output pins All output pins -IOH (-IOH) IOL Symbol IOL Min Typ Max 2 10 40 80 2 30 mA mA mA Unit mA
13.2.5
AC Characteristics (HD6433644, HD6433643, HD6433642, HD6433641, HD6433640)
Table 13.7 lists the control signal timing, and tables 13.8 and 13.9 list the serial interface timing of the HD6433644, the HD6433643, the HD6433642, the HD6433641 and the HD6433640.
Rev. 6.00 Sep 12, 2006 page 376 of 526 REJ09B0326-0600
Section 13 Electrical Characteristics
Table 13.7 Control Signal Timing VCC = 4.0 V to 5.5 V, VSS = 0.0 V, Ta = -20C to +75C, unless otherwise specified.
Applicable Pins Values Min Typ 2 tOSC tcyc fW tW tsubcyc X1, X2 X1, X2 Max 10 5 1000 ns 1000 128 25.6 tOSC s kHz s tW VCC = 2.5 V to 5.5 V VCC = 2.5 V to 5.5 V VCC = 2.5 V to 5.5 V *2 Unit MHz VCC = 2.5 V to 5.5 V *1 VCC = 2.5 V to 5.5 V Figure 13.1 VCC = 2.5 V to 5.5 V *1 Test Condition Reference Figure
Item System clock oscillation frequency OSC clock (OSC) cycle time System clock () cycle time Subclock oscillation frequency Watch clock (W ) cycle time Subclock (SUB) cycle time Instruction cycle time Oscillation stabilization time (crystal resonator) Oscillation stabilization time (ceramic resonator)
Symbol fOSC
OSC1, OSC2 2
OSC1, OSC2 100 200 2 2 2
32.768 30.5 8 40 60 20 40 2 15 20 15 20
tcyc VCC = 2.5 V to 5.5 V tsubcyc ms VCC = 2.5 V to 5.5 V ms VCC = 2.5 V to 5.5 V s ns VCC = 2.5 V to 5.5 V ns VCC = 2.5 V to 5.5 V ns VCC = 2.5 V to 5.5 V ns VCC = 2.5 V to 5.5 V tcyc VCC = 2.5 V to 5.5 V Figure 13.2 VCC = 2.5 V to 5.5 V Figure 13.1
trc
OSC1, OSC2
trc
OSC1, OSC2 X1, X2 OSC1 OSC1 40 80 40 80 RES 10
Oscillation stabilization trc time External clock high width External clock low width External clock rise time External clock fall time Pin RES low width tCPH tCPL tCPr tCPf tREL
Rev. 6.00 Sep 12, 2006 page 377 of 526 REJ09B0326-0600
Section 13 Electrical Characteristics
Applicable Pins Values Min Typ Max Unit Test Condition Reference Figure
Item Input pin high width
Symbol tIH
IRQ0 to IRQ3, 2 INT0 to INT7, ADTRG, TMIB, TMCIV, TMRIV, FTCI, FTIA, FTIB, FTIC, FTID, TRGV IRQ0 to IRQ3, 2 INT6, INT7, ADTRG, TMIB, TMCIV, TMRIV, FTCI, FTIA, FTIB, FTIC, FTID, TRGV
tcyc VCC = 2.5 V to 5.5 V Figure 13.3 tsubcyc
Input pin low width
tIL
tcyc VCC = 2.5 V to 5.5 V tsubcyc
Notes: 1. A frequency between 1 MHz to 10 MHz is required when an external clock is input. 2. Selected with SA1 and SA0 of system clock control register 2 (SYSCR2).
Rev. 6.00 Sep 12, 2006 page 378 of 526 REJ09B0326-0600
Section 13 Electrical Characteristics
Table 13.8 Serial Interface (SCI1) Timing VCC = 4.0 V to 5.5 V, VSS = 0.0 V, Ta = -20C to +75C, unless otherwise specified.
Applicable Symbol Pins tScyc tSCKH tSCKL tSCKr SCK1 SCK1 SCK1 SCK1 Values Min 2 0.4 0.4 tSCKf SCK1 SO1 SI1 180 360 tSIH SI1 180 360 Typ Max 60 80 60 80 200 350 ns VCC = 2.5 V to 5.5 V ns VCC = 2.5 V to 5.5 V ns VCC = 2.5 V to 5.5 V ns VCC = 2.5 V to 5.5 V Unit tcyc tScyc tScyc ns VCC = 2.5 V to 5.5 V Referenc Test Condition e Figure VCC = 2.5 V to 5.5 V VCC = 2.5 V to 5.5 V VCC = 2.5 V to 5.5 V Figure 13.4
Item Input serial clock cycle time Input serial clock high width Input serial clock low width Input serial clock rise time Input serial clock fall time
Serial output data tSOD delay time Serial input data setup time Serial input data hold time tSIS
Rev. 6.00 Sep 12, 2006 page 379 of 526 REJ09B0326-0600
Section 13 Electrical Characteristics
Table 13.9 Serial Interface (SCI3) Timing VCC = 2.5 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = 0.0 V, Ta = -20C to +75C, unless otherwise specified.
Values Item Input clock cycle Synchronous tSCKW tTXD Symbol Min Asynchronous tScyc 4 6 0.4 Receive data setup time (synchronous) Receive data hold time (synchronous) tRXS Typ Max 0.6 1 1 ns VCC = 4.0 V to 5.5 V ns VCC = 4.0 V to 5.5 V tScyc tcyc VCC = 4.0 V to 5.5 V Figure 13.6 Reference Unit Test Condition Figure tcyc Figure 13.5
Input clock pulse width Transmit data delay time (synchronous)
200.0 400.0
tRXH
200.0 400.0
Rev. 6.00 Sep 12, 2006 page 380 of 526 REJ09B0326-0600
Section 13 Electrical Characteristics
13.2.6
A/D Converter Characteristics
Table 13.10 shows the A/D converter characteristics of the HD6473644, the HD6433644, the HD6433643, the HD6433642, the HD6433641 and the HD6433640. Table 13.10 A/D Converter Characteristics VCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C, unless otherwise specified.
Applicable Symbol Pins Min AVCC 2.7 Values Typ Max 5.5 Unit V Test Condition Reference Figure *1
Item
Analog power AVCC supply voltage Analog input voltage AVin
AN0 to AN7 AVCC AVCC
AVSS -0.3
150.0
AVCC +0.3 1.5
V mA A AVCC = 5 V *2 Reference value *3
Analog power AIOPE supply AISTOP1 current AISTOP2 Analog input capacitance CAin
AVCC AN0 to AN7

5.0 30.0 5.0
A pF k
RAin Allowable signal source impedance Resolution Nonlinearity error Quantization error Absolute accuracy Conversion time
12.4

8 2.0 0.5 2.5 124
bit LSB LSB LSB s
Notes: 1. Set AVCC = VCC when the A/D converter is not used. 2. AISTOP1 is the current in active and sleep modes while the A/D converter is idle. 3. AISTOP2 is the current at reset and in standby, watch, subactive, and subsleep modes while the A/D converter is idle.
Rev. 6.00 Sep 12, 2006 page 381 of 526 REJ09B0326-0600
Section 13 Electrical Characteristics
13.3
13.3.1
Electrical Characteristics (ZTAT and R of the Mask ROM Version)
Power Supply Voltage and Operating Range
The power supply voltage and operating range are indicated by the shaded region in the figures below. 1. Power supply voltage vs. oscillator frequency range
16.0 32.768
f OSC (MHz)
2.0 2.7*1 2.7*1
4.0
5.5 VCC (V)
fw (kHz)
10.0
4.0
5.5 VCC (V)
* Active mode (high speed) * Sleep mode (high speed)
* All operating modes
Rev. 6.00 Sep 12, 2006 page 382 of 526 REJ09B0326-0600
Section 13 Electrical Characteristics
2.
Power supply voltage vs. clock frequency range
(MHz)
5.0
SUB (kHz)
2.7*1
8.0
16.384
8.192 4.096
0.5 4.0 5.5 VCC (V) 2.7*1 4.0 5.5 VCC (V)
* Active (high speed) mode * Sleep (high speed) mode (except CPU)
* Subactive mode * Subsleep mode (except CPU) * Watch mode (except CPU)
1000.00 625.00
(kHz)
39.0625 7.8125
2.7*1
4.0
5.5 VCC (V)
* Active (medium speed) mode * Sleep (medium speed) mode (except CPU)
Rev. 6.00 Sep 12, 2006 page 383 of 526 REJ09B0326-0600
Section 13 Electrical Characteristics
3. Analog power supply voltage vs. A/D converter operating range
8.0
(MHz)
5.0
Do not exceed the maximum conversion time value.
0.5 2.7*2 4.0 5.5 AVCC (V) * Active (medium speed) mode * Sleep (medium speed) mode
* Active (high speed) mode * Sleep (high speed) mode
Notes: 1. 2.5 V for HD6433644R, HD6433643R, HD6433642R, HD6433641R and HD6433640R. 2. AD conversion is guaranteed with 2.5 V.
Rev. 6.00 Sep 12, 2006 page 384 of 526 REJ09B0326-0600
Section 13 Electrical Characteristics
13.3.2
DC Characteristics (HD6473644R)
Table 13.11 lists the DC characteristics of the HD6473644R. Table 13.11 DC Characteristics VCC = 4.0 V to 5.5 V, VSS = 0.0 V, Ta = -20C to +75C unless otherwise indicated.
Applicable Symbol Pins Values Min Typ Max VCC +0.3 Unit Test Condition V Notes
Item
Input high VIH voltage
RES, 0.8 VCC INT0 to INT7, IRQ0 to IRQ3, ADTRG, TMIB, TMRIV, TMCIV, 0.9 VCC FTCI, FTIA, FTIB, FTIC, FTID, SCK1, SCK3, TRGV SI1, RXD, 0.7 VCC P10, P14 to P17, P20 to P22, P30 to P32, P50 to P57, 0.8 VCC P60 to P67, P73 to P77, P80 to P87, P90 to P94 PB0 to PB7 0.7 VCC 0.8 VCC
VCC +0.3
VCC = 2.7 V to 5.5 V including subactive mode V
VCC +0.3
VCC +0.3
VCC = 2.7 V to 5.5 V including subactive mode

AVCC +0.3 V AVCC +0.3 VCC = 2.7 V to 5.5 V including subactive mode V VCC = 2.7 V to 5.5 V including subactive mode
OSC1
VCC -0.5 VCC -0.3
VCC +0.3 VCC +0.3
Note: Connect the TEST pin to VSS.
Rev. 6.00 Sep 12, 2006 page 385 of 526 REJ09B0326-0600
Section 13 Electrical Characteristics Applicable Symbol Pins Values Min Typ Max 0.2 VCC Unit Test Condition V Notes
Item
Input low VIL voltage
-0.3 RES, INT0 to INT7, IRQ0 to IRQ3, ADTRG, TMIB, TMRIV, TMCIV, FTCI, FTIA, -0.3 FTIB, FTIC, FTID, SCK1, SCK3, TRGV -0.3 SI1, RXD, P10, P14 to P17, P20 to P22, P30 to P32, P50 to P57, P60 to P67, -0.3 P73 to P77, P80 to P87, P90 to P94, PB0 to PB7 OSC1 -0.3 -0.3
0.1 VCC
VCC = 2.7 V to 5.5 V including subactive mode V
0.3 VCC
0.2 VCC
VCC = 2.7 V to 5.5 V including subactive mode V VCC = 2.7 V to 5.5 V including subactive mode

0.5 0.3
Rev. 6.00 Sep 12, 2006 page 386 of 526 REJ09B0326-0600
Section 13 Electrical Characteristics Applicable Symbol Pins VOH Values Min Typ Max Unit V Test Condition Notes -IOH = 1.5 mA
Item Output high voltage
P10, P14 to P17, VCC -1.0 P20 to P22, P30 to P32, P50 to P57, VCC -0.5 P60 to P67, P73 to P77, P80 to P87, P90 to P94 P10, P14 to P17, P20 to P22, P30 to P32, P50 to P57, P73 to P77, P80 to P87, P90 to P94 P60 to P67
VCC = 2.7 V to 5.5 V -IOH = 0.1 mA
Output low voltage
VOL
0.6
V
IOL = 1.6 mA
0.4
VCC = 2.7 V to 5.5 V IOL = 0.4 mA V IOL = 10.0 mA IOL = 1.6 mA VCC = 2.7 V to 5.5 V IOL = 0.4 mA A Vin = 0.5 V to (VCC -0.5 V)

1.0 0.4 0.4
Input/ output leakage current
| IIL |
OSC1, P10, P14 to P17, P20 to P22, P30 to P32, P50 to P57, P60 to P67, P73 to P77, P80 to P87, P90 to P94 PB0 to PB7
1.0

1.0 20
A A
Vin = 0.5 V to (AVCC -0.5 V) Vin = 0.5 V to (VCC -0.5 V) VCC = 5 V, Vin = 0 V VCC = 2.7 V, Vin = 0 V Reference value
Input leakage current Pull-up MOS current
| IIL |
RES, IRQ0
-Ip
P10, P14 to P17, 50 P30 to P32, P50 to P57
25
300
A
Rev. 6.00 Sep 12, 2006 page 387 of 526 REJ09B0326-0600
Section 13 Electrical Characteristics Values Item Input capacitance Symbol Applicable Pins Cin All input pins except RES RES IRQ0 Active IOPE1 mode current dissipation VCC Min Typ 15 Max 15.0 60.0 30.0 20 mA Active (highspeed) mode VCC = 5 V, fOSC = 16 MHz VCC = 2.7 V, fOSC = 10 MHz mA 1, 2 Unit pF Test Condition Notes f = 1 MHz, Vin = 0 V, Ta = 25C
5
1, 2 Reference value
IOPE2
VCC
3
5
Active (medium- 1, 2 speed) mode VCC = 5 V, fOSC = 16 MHz VCC = 2.7 V, fOSC = 10 MHz 1, 2 Reference value 1, 2
1
Sleep ISLEEP1 mode current dissipation
VCC
6
10
mA
Sleep (highspeed) mode VCC = 5 V, fOSC = 16 MHz VCC = 2.7 V, fOSC = 10 MHz
2
1, 2 Reference value
ISLEEP2
VCC
2
4
mA
Sleep (medium- 1, 2 speed) mode VCC = 5 V, fOSC = 16 MHz VCC = 2.7 V, fOSC = 10 MHz 1, 2 Reference value 1, 2
1
Subactive ISUB mode current dissipation
VCC
10
20
A
VCC = 2.7 V 32-kHz crystal resonator (SUB = W /2) VCC = 2.7 V 32-kHz crystal resonator (SUB = W /8)
10
1, 2 Reference value
Rev. 6.00 Sep 12, 2006 page 388 of 526 REJ09B0326-0600
Section 13 Electrical Characteristics Applicable Pins VCC Values Min Typ 5 Max 10 Unit A Test Condition VCC = 2.7 V 32-kHz crystal resonator (SUB = W /2) VCC = 2.7 V 32-kHz crystal resonator 32-kHz crystal resonator not used Notes 1, 2
Item
Symbol
Subsleep ISUBSP mode current dissipation Watch mode current dissipation IWATCH
VCC
6
A
1, 2
ISTBY Standby mode current dissipation RAM data retaining voltage VRAM
VCC
5
A
1, 2
VCC
2
V
Notes: 1. Pin states during current measurement are given below. Mode Active (high-speed) mode Active (mediumspeed) mode Sleep (high-speed) mode Sleep (mediumspeed) mode Subactive mode Subsleep mode VCC VCC VCC RES Pin Internal State VCC Operates Operates (OSC/128) Only timers operate Only timers operate (OSC/128) Operates Only timers operate, CPU stops Only time base operates, CPU stops CPU and timers both stop VCC VCC System clock oscillator: ceramic or crystal Subclock oscillator: crystal VCC Other Pins Oscillator Pins VCC System clock oscillator: ceramic or crystal Subclock oscillator: Pin X1 = VCC
Watch mode
VCC
VCC
Standby mode
VCC
VCC
System clock oscillator: ceramic or crystal Subclock oscillator: Pin X1 = VCC
2. Excludes current in pull-up MOS transistors and output buffers.
Rev. 6.00 Sep 12, 2006 page 389 of 526 REJ09B0326-0600
Section 13 Electrical Characteristics Values Item Allowable output low current (per pin) Allowable output low current (total) Allowable output high current (per pin) Allowable output high current (total) Output pins except port 6 Port 6 Output pins except port 6 Port 6 All output pins All output pins -IOH (-IOH) IOL Symbol IOL Min Typ Max 2 10 40 80 2 30 mA mA mA Unit mA
Rev. 6.00 Sep 12, 2006 page 390 of 526 REJ09B0326-0600
Section 13 Electrical Characteristics
13.3.3
AC Characteristics (HD6473644R)
Table 13.12 lists the control signal timing, and tables 13.13 and 13.14 list the serial interface timing of the HD6473644R. Table 13.12 Control Signal Timing VCC = 4.0 V to 5.5 V, VSS = 0.0 V, Ta = -20C to +75C, unless otherwise specified.
Applicable Pins Values Min 2 tOSC tcyc fW tW tsubcyc X1, X2 X1, X2 OSC1, OSC2 62.5 100 2 2 2 trc OSC1, OSC2 trc OSC1, OSC2 X1, X2 OSC1 OSC1 20 40 tCPL tCPr tCPf 20 40 Typ Max 16 10 1000 ns 1000 128 25.6 tOSC s kHz s tW VCC = 2.7 V to 5.5 V VCC = 2.7 V to 5.5 V VCC = 2.7 V to 5.5 V *2 VCC = 2.7 V to 5.5 V Unit MHz VCC = 2.7 V to 5.5 V *1 Figure 13.1 Test Condition Reference Figure
Item System clock oscillation frequency OSC clock (OSC) cycle time System clock () cycle time Subclock oscillation frequency Watch clock (W ) cycle time Subclock (SUB) cycle time Instruction cycle time Oscillation stabilization time (crystal resonator) Oscillation stabilization time (ceramic resonator)
Symbol fOSC
OSC1, OSC2 2
VCC = 2.7 V to 5.5 V *1
32.76 8 30.5 8 40 60 20 40 2 15 15
tcyc VCC = 2.7 V to 5.5 V tsubcyc ms VCC = 2.7 V to 5.5 V ms VCC = 2.7 V to 5.5 V s ns VCC = 2.7 V to 5.5 V ns VCC = 2.7 V to 5.5 V ns ns VCC = 2.7 V to 5.5 V VCC = 2.7 V to 5.5 V VCC = 2.7 V to 5.5 V Figure 13.1
Oscillation stabilization trc time External clock high width External clock low width External clock rise time External clock fall time tCPH
Rev. 6.00 Sep 12, 2006 page 391 of 526 REJ09B0326-0600
Section 13 Electrical Characteristics
Applicable Pins RES Values Min 10 Typ Max Unit tcyc Test Condition Reference Figure
Item Pin RES low width Input pin high level width
Symbol tREL tIH
VCC = 2.7 V to 5.5 V Figure 13.2
IRQ0 to IRQ3, 2 INT0 to INT7, ADTRG, TMIB, TMCIV, TMRIV, FTCI, FTIA, FTIB, FTIC, FTID, TRGV IRQ0 to IRQ3, 2 INT6, INT7, ADTRG, TMIB, TMCIV, TMRIV, FTCI, FTIA, FTIB, FTIC, FTID, TRGV
tcyc VCC = 2.7 V to 5.5 V Figure 13.3 tsubcyc
Input pin low level width
tIL
tcyc VCC = 2.7 V to 5.5 V tsubcyc
Notes: 1. A frequency between 1 MHz to 10 MHz is required when an external clock is input. 2. Selected with SA1 and SA0 of system clock control register 2 (SYSCR2).
Rev. 6.00 Sep 12, 2006 page 392 of 526 REJ09B0326-0600
Section 13 Electrical Characteristics
Table 13.13 Serial Interface (SCI1) Timing VCC = 4.0 V to 5.5 V, VSS = 0.0 V, Ta = -20C to +75C, unless otherwise specified.
Applicable Symbol Pins tScyc tSCKH tSCKL tSCKr SCK1 SCK1 SCK1 SCK1 Values Min 2 0.4 0.4 tSCKf SCK1 SO1 SI1 180 360 tSIH SI1 180 360 Typ Max 60 80 60 80 200 350 ns VCC = 2.7 V to 5.5 V ns VCC = 2.7 V to 5.5 V ns VCC = 2.7 V to 5.5 V ns VCC = 2.7 V to 5.5 V Unit Test Condition tcyc tScyc tScyc ns VCC = 2.7 V to 5.5 V VCC = 2.7 V to 5.5 V VCC = 2.7 V to 5.5 V VCC = 2.7 V to 5.5 V Reference Figure Figure 13.4
Item Input serial clock cycle time Input serial clock high width Input serial clock low width Input serial clock rise time Input serial clock fall time
Serial output data tSOD delay time Serial input data setup time Serial input data hold time tSIS
Rev. 6.00 Sep 12, 2006 page 393 of 526 REJ09B0326-0600
Section 13 Electrical Characteristics
Table 13.14 Serial Interface (SCI3) Timing VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = 0.0 V, Ta = -20C to +75C, unless otherwise specified.
Values Item Input clock cycle Synchronous tSCKW tTXD Symbol Asynchronous tScyc Min 4 6 0.4 Receive data setup time (synchronous) Receive data hold time (synchronous) tRXS Typ Max 0.6 1 1 ns VCC = 4.0 V to 5.5 V ns VCC = 4.0 V to 5.5 V tScyc tcyc VCC = 4.0 V to 5.5 V Figure 13.6 Unit Test Condition tcyc Reference Figure Figure 13.5
Input clock pulse width Transmit data delay time (synchronous)
200.0 400.0
tRXH
200.0 400.0
Rev. 6.00 Sep 12, 2006 page 394 of 526 REJ09B0326-0600
Section 13 Electrical Characteristics
13.3.4
DC Characteristics (HD6433644R, HD6433643R, HD6433642R, HD6433641R, HD6433640R)
Table 13.15 lists the DC characteristics of the HD6433644R, the HD6433643R, the HD6433642R, the HD6433641R and the HD6433640R. Table 13.15 DC Characteristics VCC = 4.0 V to 5.5 V, VSS = 0.0 V, Ta = -20C to +75C unless otherwise indicated.
Applicable Symbol Pins Values Min Typ Max VCC +0.3 Unit Test Condition V Notes
Item
Input high VIH voltage
RES, 0.8 VCC INT0 to INT7, IRQ0 to IRQ3, ADTRG, TMIB, TMRIV, TMCIV, 0.9 VCC FTCI, FTIA, FTIB, FTIC, FTID, SCK1, SCK3, TRGV SI1, RXD, 0.7 VCC P10, P14 to P17, P20 to P22, P30 to P32, P50 to P57, 0.8 VCC P60 to P67, P73 to P77, P80 to P87, P90 to P94 PB0 to PB7 0.7 VCC 0.8 VCC
VCC +0.3
VCC = 2.5 V to 5.5 V including subactive mode V
VCC +0.3
VCC +0.3
VCC = 2.5 V to 5.5 V including subactive mode

AVCC +0.3 V AVCC +0.3 VCC = 2.5 V to 5.5 V including subactive mode V VCC = 2.5 V to 5.5 V including subactive mode
OSC1
VCC -0.5 VCC -0.3
VCC +0.3 VCC +0.3
Note: Connect the TEST pin to VSS.
Rev. 6.00 Sep 12, 2006 page 395 of 526 REJ09B0326-0600
Section 13 Electrical Characteristics Applicable Symbol Pins Values Min Typ Max 0.2 VCC Unit Test Condition V Notes
Item
Input low VIL voltage
-0.3 RES, INT0 to INT7, IRQ0 to IRQ3, ADTRG, TMIB, TMRIV, TMCIV, FTCI, FTIA, -0.3 FTIB, FTIC, FTID, SCK1, SCK3, TRGV -0.3 SI1, RXD, P10, P14 to P17, P20 to P22, P30 to P32, P50 to P57, P60 to P67, -0.3 P73 to P77, P80 to P87, P90 to P94, PB0 to PB7 OSC1 -0.3 -0.3
0.1 VCC
VCC = 2.5 V to 5.5 V including subactive mode V
0.3 VCC
0.2 VCC
VCC = 2.5 V to 5.5 V including subactive mode V VCC = 2.5 V to 5.5 V including subactive mode

0.5 0.3
Rev. 6.00 Sep 12, 2006 page 396 of 526 REJ09B0326-0600
Section 13 Electrical Characteristics Applicable Symbol Pins VOH Values Min Typ Max Unit V Test Condition Notes -IOH = 1.5 mA
Item Output high voltage
P10, P14 to P17, VCC -1.0 P20 to P22, P30 to P32, P50 to P57, VCC -0.5 P60 to P67, P73 to P77, P80 to P87, P90 to P94 P10, P14 to P17, P20 to P22, P30 to P32, P50 to P57, P73 to P77, P80 to P87, P90 to P94 P60 to P67
VCC = 2.5 V to 5.5 V -IOH = 0.1 mA
Output low voltage
VOL
0.6
V
IOL = 1.6 mA
0.4
VCC = 2.5 V to 5.5 V IOL = 0.4 mA V IOL = 10.0 mA IOL = 1.6 mA VCC = 2.5 V to 5.5 V IOL = 0.4 mA A Vin = 0.5 V to (VCC -0.5 V)

1.0 0.4 0.4
Input/ output leakage current
| IIL |
OSC1, P10, P14 to P17, P20 to P22, P30 to P32, P50 to P57, P60 to P67, P73 to P77, P80 to P87, P90 to P94 PB0 to PB7
1.0

1.0 1
A A
Vin = 0.5 V to (AVCC -0.5 V) Vin = 0.5 V to (VCC -0.5 V) VCC = 5 V, Vin = 0 V VCC = 2.5 V, Vin = 0 V Reference value
Input leakage current Pull-up MOS current
| IIL |
RES, IRQ0
-Ip
P10, P14 to P17, 50 P30 to P32, P50 to P57
25
300
A
Rev. 6.00 Sep 12, 2006 page 397 of 526 REJ09B0326-0600
Section 13 Electrical Characteristics Applicable Symbol Pins Cin All input pins except RES RES IRQ0 Active IOPE1 mode current dissipation VCC Values Min Typ 15 Max 15.0 15.0 15.0 20 mA Active (highspeed) mode VCC = 5 V, fOSC = 16 MHz VCC = 2.5 V, fOSC = 10 MHz mA Active (mediumspeed) mode VCC = 5 V, fOSC = 16 MHz VCC = 2.5 V, fOSC = 10 MHz mA Sleep (highspeed) mode VCC = 5 V, fOSC = 16 MHz VCC = 2.5 V, fOSC = 10 MHz mA Sleep (mediumspeed) mode VCC = 5 V, fOSC = 16 MHz VCC = 2.5 V, fOSC = 10 MHz A VCC = 2.5 V 32-kHz crystal resonator (SUB = W /2) VCC = 2.5 V 32-kHz crystal resonator (SUB = W /8) 1, 2 Unit pF Test Condition f = 1 MHz, Vin = 0 V, Ta = 25C Notes
Item Input capacitance
5
1, 2 Reference value 1, 2
IOPE2
VCC
3
5
1
1, 2 Reference value 1, 2
Sleep ISLEEP1 mode current dissipation
VCC
6
10
2
1, 2 Reference value 1, 2
ISLEEP2
VCC
2
4
1
1, 2 Reference value 1, 2
Subactive ISUB mode current dissipation
VCC
10
20
10
1, 2 Reference value
Rev. 6.00 Sep 12, 2006 page 398 of 526 REJ09B0326-0600
Section 13 Electrical Characteristics Applicable Symbol Pins VCC Values Min Typ 5 Max 10 Unit Test Condition A VCC = 2.5 V 32-kHz crystal resonator (SUB = W /2) VCC = 2.5 V 32-kHz crystal resonator 32-kHz crystal resonator not used Notes 1, 2
Item
Subsleep ISUBSP mode current dissipation Watch IWATCH mode current dissipation Standby ISTBY mode current dissipation RAM data VRAM retaining voltage
VCC
6
A
1, 2
VCC
5
A
1, 2
VCC
2
V
Notes: 1. Pin states during current measurement are given below. Mode RES Pin Internal State Operates Operates (OSC/128) VCC Only timers operate VCC Only timers operate (OSC/128) VCC VCC VCC Operates VCC Only timers operate, VCC CPU stops Only time base operates, CPU stops CPU and timers both stop VCC System clock oscillator: ceramic or crystal Subclock oscillator: crystal System clock oscillator: ceramic or crystal Subclock oscillator: Pin X1 = VCC 2. Excludes current in pull-up MOS transistors and output buffers. Rev. 6.00 Sep 12, 2006 page 399 of 526 REJ09B0326-0600 Other Pins Oscillator Pins VCC System clock oscillator: ceramic or crystal Subclock oscillator: Pin X1 = VCC
Active (high-speed) VCC mode Active (mediumspeed) mode Sleep (high-speed) mode Sleep (mediumspeed) mode Subactive mode Subsleep mode Watch mode
Standby mode
VCC
VCC
Section 13 Electrical Characteristics Values Item Allowable output low current (per pin) Allowable output low current (total) Allowable output high current (per pin) Allowable output high current (total) Output pins except port 6 Port 6 Output pins except port 6 Port 6 All output pins All output pins -IOH (-IOH) IOL Symbol IOL Min Typ Max 2 10 40 80 2 30 mA mA mA Unit mA
13.3.5
AC Characteristics (HD6433644R, HD6433643R, HD6433642R, HD6433641R, HD6433640R)
Table 13.16 lists the control signal timing, and tables 13.17 and 13.18 list the serial interface timing of the HD6433644R, the HD6433643R, the HD6433642R, the HD6433641R and the HD6433640R.
Rev. 6.00 Sep 12, 2006 page 400 of 526 REJ09B0326-0600
Section 13 Electrical Characteristics
Table 13.16 Control Signal Timing VCC = 4.0 V to 5.5 V, VSS = 0.0 V, Ta = -20C to +75C, unless otherwise specified.
Applicable Pins Values Min Typ 2 tOSC tcyc fW tW tsubcyc X1, X2 X1, X2 Max 16 10 1000 ns 1000 128 25.6 tOSC s kHz s tW VCC = 2.5 V to 5.5 V VCC = 2.5 V to 5.5 V VCC = 2.5 V to 5.5 V *2 Unit MHz VCC = 2.5 V to 5.5 V *1 VCC = 2.5 V to 5.5 V Figure 13.1 VCC = 2.5 V to 5.5 V *1 Test Condition Reference Figure
Item System clock oscillation frequency OSC clock (OSC) cycle time System clock () cycle time Subclock oscillation frequency Watch clock (W ) cycle time Subclock (SUB) cycle time Instruction cycle time Oscillation stabilization time (crystal resonator) Oscillation stabilization time (ceramic resonator)
Symbol fOSC
OSC1, OSC2 2
OSC1, OSC2 62.5 100 2 2 2
32.768 30.5 8 40 60 20 40 2 15 15
tcyc VCC = 2.5 V to 5.5 V tsubcyc ms VCC = 2.5 V to 5.5 V ms VCC = 2.5 V to 5.5 V s ns VCC = 2.5 V to 5.5 V ns VCC = 2.5 V to 5.5 V ns ns tcyc VCC = 2.5 V to 5.5 V VCC = 2.5 V to 5.5 V VCC = 2.5 V to 5.5 V Figure 13.2 VCC = 2.5 V to 5.5 V Figure 13.1
trc
OSC1, OSC2
trc
OSC1, OSC2 X1, X2 OSC1 OSC1 20 40 20 40 RES 10
Oscillation stabilization trc time External clock high width External clock low width External clock rise time External clock fall time Pin RES low width tCPH tCPL tCPr tCPf tREL
Rev. 6.00 Sep 12, 2006 page 401 of 526 REJ09B0326-0600
Section 13 Electrical Characteristics
Applicable Pins Values Min Typ Max Unit Test Condition Reference Figure
Item Input pin high width
Symbol tIH
IRQ0 to IRQ3, 2 INT0 to INT7, ADTRG, TMIB, TMCIV, TMRIV, FTCI, FTIA, FTIB, FTIC, FTID, TRGV IRQ0 to IRQ3, 2 INT6, INT7, ADTRG, TMIB, TMCIV, TMRIV, FTCI, FTIA, FTIB, FTIC, FTID, TRGV
tcyc VCC = 2.5 V to 5.5 V Figure 13.3 tsubcyc
Input pin low width
tIL
tcyc VCC = 2.5 V to 5.5 V tsubcyc
Notes: 1. A frequency between 1 MHz to 10 MHz is required when an external clock is input. 2. Selected with SA1 and SA0 of system clock control register 2 (SYSCR2).
Rev. 6.00 Sep 12, 2006 page 402 of 526 REJ09B0326-0600
Section 13 Electrical Characteristics
Table 13.17 Serial Interface (SCI1) Timing VCC = 4.0 V to 5.5 V, VSS = 0.0 V, Ta = -20C to +75C, unless otherwise specified.
Applicable Symbol Pins tScyc tSCKH tSCKL tSCKr SCK1 SCK1 SCK1 SCK1 Values Min 2 0.4 0.4 tSCKf SCK1 SO1 SI1 180 360 tSIH SI1 180 360 Typ Max 60 80 60 80 200 350 ns VCC = 2.5 V to 5.5 V ns VCC = 2.5 V to 5.5 V ns VCC = 2.5 V to 5.5 V ns VCC = 2.5 V to 5.5 V Unit Test Condition tcyc tScyc tScyc ns VCC = 2.5 V to 5.5 V VCC = 2.5 V to 5.5 V VCC = 2.5 V to 5.5 V VCC = 2.5 V to 5.5 V Reference Figure Figure 13.4
Item Input serial clock cycle time Input serial clock high width Input serial clock low width Input serial clock rise time Input serial clock fall time
Serial output data tSOD delay time Serial input data setup time Serial input data hold time tSIS
Rev. 6.00 Sep 12, 2006 page 403 of 526 REJ09B0326-0600
Section 13 Electrical Characteristics
Table 13.18 Serial Interface (SCI3) Timing VCC = 2.5 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = 0.0 V, Ta = -20C to +75C, unless otherwise specified.
Values Item Input clock cycle Synchronous tSCKW tTXD Symbol Asynchronous tScyc Min 4 6 0.4 Receive data setup time (synchronous) Receive data hold time (synchronous) tRXS Typ Max 0.6 1 1 ns VCC = 4.0 V to 5.5 V ns VCC = 4.0 V to 5.5 V tScyc tcyc VCC = 4.0 V to 5.5 V Figure 13.6 Unit Test Condition tcyc Reference Figure Figure 13.5
Input clock pulse width Transmit data delay time (synchronous)
200.0 400.0
tRXH
200.0 400.0
Rev. 6.00 Sep 12, 2006 page 404 of 526 REJ09B0326-0600
Section 13 Electrical Characteristics
13.3.6
A/D Converter Characteristics
Table 13.19 shows the A/D converter characteristics of the HD6473644R, the HD6433644R, the HD6433643R, the HD6433642R, the HD6433641R and the HD6433640R. Table 13.19 A/D Converter Characteristics VCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C, unless otherwise specified.
Applicable Symbol Pins Min AVCC AVin AIOPE AISTOP1 AVCC AN0 to AN7 AVCC AVCC 2.7 AVSS -0.3 Values Typ 150.0 Max 5.5 AVCC +0.3 1.5 Test Unit Condition V V mA A AVCC = 5 V *2 Reference value *3 Reference Figure *1
Item Analog power supply voltage Analog input voltage Analog power supply current
AISTOP2 Analog input capacitance CAin
AVCC AN0 to AN7

5.0 30.0 5.0
A pF k
Allowable signal RAin source impedance Resolution Nonlinearity error Quantization error Absolute accuracy Conversion time
7.75

8 2.0 0.5 2.5 124
bit LSB LSB LSB s
Notes: 1. Set AVCC = VCC when the A/D converter is not used. 2. AISTOP1 is the current in active and sleep modes while the A/D converter is idle. 3. AISTOP2 is the current at reset and in standby, watch, subactive, and subsleep modes while the A/D converter is idle.
Rev. 6.00 Sep 12, 2006 page 405 of 526 REJ09B0326-0600
Section 13 Electrical Characteristics
13.4
13.4.1
Electrical Characteristics (F-ZTAT version)
Power Supply Voltage and Operating Range
The power supply voltage and operating range are indicated by the shaded region in the figures below. 1. Power supply voltage vs. oscillator frequency range
16.0 32.768
f OSC (MHz)
2.0
fw (kHz)
10.0
3.0
4.0
5.5 VCC (V)
3.0
4.0
5.5 VCC (V)
* Active mode (high speed) * Sleep mode (high speed)
* All operating modes
Rev. 6.00 Sep 12, 2006 page 406 of 526 REJ09B0326-0600
Section 13 Electrical Characteristics
2. Power supply voltage vs. clock frequency range
(MHz)
5.0
SUB (kHz)
3.0 4.0 5.5 VCC (V)
8.0
16.384
8.192 4.096
0.5 3.0 4.0 5.5 VCC (V)
* Active (high speed) mode * Sleep (high speed) mode (except CPU)
* Subactive mode * Subsleep mode (except CPU) * Watch mode (except CPU)
1000.00 625.00
(kHz)
39.0625 7.8125
3.0
4.0
5.5 VCC (V)
* Active (medium speed) mode * Sleep (medium speed) mode (except CPU)
Rev. 6.00 Sep 12, 2006 page 407 of 526 REJ09B0326-0600
Section 13 Electrical Characteristics
3. Analog power supply voltage vs. A/D converter operating range
8.0
(MHz)
5.0
Do not exceed the maximum conversion time value.
0.5 3.0 4.0 5.5 AVCC (V) * Active (medium speed) mode * Sleep (medium speed) mode
* Active (high speed) mode * Sleep (high speed) mode
Rev. 6.00 Sep 12, 2006 page 408 of 526 REJ09B0326-0600
Section 13 Electrical Characteristics
13.4.2
DC Characteristics (HD64F3644, HD64F3643, HD64F3642A)
Table 13.20 lists the DC characteristics of the HD64F3644, HD64F3643, and HD64F3642A. Table 13.20 DC Characteristics VCC = 4.0 V to 5.5 V, VSS = 0.0 V, Ta = -20C to +75C unless otherwise indicated.
Applicable Symbol Pins Values Min Typ Max VCC +0.3 Unit Test Condition V Notes
Item
Input high VIH voltage
RES, 0.8 VCC INT0 to INT7, IRQ0 to IRQ3, ADTRG, TMIB, TMRIV, TMCIV, 0.9 VCC FTCI, FTIA, FTIB, FTIC, FTID, SCK1, SCK3, TRGV SI1, RXD, 0.7 VCC P10, P14 to P17, P20 to P22, P30 to P32, P50 to P57, 0.8 VCC P60 to P67, P73 to P77, P80 to P87, P91 to P94 PB0 to PB7 0.7 VCC 0.8 VCC
VCC +0.3
VCC = 3.0 V to 5.5 V including subactive mode V
VCC +0.3
VCC +0.3
VCC = 3.0 V to 5.5 V including subactive mode

AVCC +0.3 V AVCC +0.3 VCC = 3.0 V to 5.5 V including subactive mode V VCC = 3.0 V to 5.5 V including subactive mode
OSC1
VCC -0.5 VCC -0.3
VCC +0.3 VCC +0.3
Note: Except in boot mode, connect the TEST pin to VSS.
Rev. 6.00 Sep 12, 2006 page 409 of 526 REJ09B0326-0600
Section 13 Electrical Characteristics Applicable Symbol Pins Values Min Typ Max 0.2 VCC Unit Test Condition V Notes
Item
Input low VIL voltage
RES, -0.3 INT0 to INT7, IRQ0 to IRQ3, ADTRG, TMIB, TMRIV, TMCIV, -0.3 FTCI, FTIA, FTIB, FTIC, FTID, SCK1, SCK3, TRGV -0.3 SI1, RXD, P10, P14 to P17, P20 to P22, P30 to P32, P50 to P57, P60 to P67, -0.3 P73 to P77, P80 to P87, P91 to P94, PB0 to PB7 OSC1 -0.3 -0.3
0.1 VCC
VCC = 3.0 V to 5.5 V including subactive mode V
0.3 VCC
0.2 VCC
VCC = 3.0 V to 5.5 V including subactive mode V VCC = 3.0 V to 5.5 V including subactive mode

0.5 0.3
Rev. 6.00 Sep 12, 2006 page 410 of 526 REJ09B0326-0600
Section 13 Electrical Characteristics Applicable Symbol Pins VOH Values Min Typ Max Unit Test Condition Notes V -IOH = 1.5 mA
Item Output high voltage
P10, P14 to P17, VCC -1.0 P20 to P22, P30 to P32, P50 to P57, VCC -0.5 P60 to P67, P73 to P77, P80 to P87, P91 to P94 P10, P14 to P17, P20 to P22, P30 to P32, P50 to P57, P73 to P77, P80 to P87, P91 to P94 P60 to P67
VCC = 3.0 V to 5.5 V -IOH = 0.1 mA
Output low voltage
VOL
0.6
V
IOL = 1.6 mA
0.4
VCC = 3.0 V to 5.5 V IOL = 0.4 mA V IOL = 10.0 mA IOL = 1.6 mA VCC = 2.7 V to 5.5 V IOL = 0.4 mA A Vin = 0.5 V to (VCC -0.5 V)

1.0 0.4 0.4
Input/ output leakage current
| IIL |
OSC1, RES, P10, P14 to P17, P20 to P22, P30 to P32, P50 to P57, P60 to P67, P73 to P77, P80 to P87, P91 to P94 PB0 to PB7
1.0

1.0 20
A A
Vin = 0.5 V to (AVCC -0.5 V) Vin = 0.5 V to (VCC -0.5 V) VCC = 5 V, Vin = 0 V VCC = 3.0 V, Vin = 0 V Reference value
Input leakage current Pull-up MOS current
| IIL |
IRQ0, TEST
-Ip
P10, P14 to P17, 50 P30 to P32, P50 to P57
35
300
A
Rev. 6.00 Sep 12, 2006 page 411 of 526 REJ09B0326-0600
Section 13 Electrical Characteristics Applicable Symbol Pins Cin All input pins except TEST IRQ0, TEST VCC Values Min Typ 15 Max 15.0 30.0 25 mA Unit pF Test Condition Notes f = 1 MHz, Vin = 0 V, Ta = 25C Active (highspeed) mode VCC = 5 V, fOSC = 16 MHz VCC = 3.0 V, fOSC = 10 MHz mA 1, 2
Item Input capacitance
Active IOPE1 mode current dissipation
8.5
1, 2 Reference value
IOPE2
VCC
3
5
Active (medium- 1, 2 speed) mode VCC = 5 V, fOSC = 16 MHz VCC = 3.0 V, fOSC = 10 MHz 1, 2 Reference value 1, 2
2
Sleep ISLEEP1 mode current dissipation
VCC
6
10
mA
Sleep (highspeed) mode VCC = 5 V, fOSC = 16 MHz VCC = 3.0 V, fOSC = 10 MHz
3.5
1, 2 Reference value
ISLEEP2
VCC
2
4
mA
Sleep (medium- 1, 2 speed) mode VCC = 5 V, fOSC = 16 MHz VCC = 3.0 V, fOSC = 10 MHz 1, 2 Reference value 1, 2
1
Subactive ISUB mode current dissipation
VCC
1
2
mA
VCC = 3.0 V 32-kHz crystal resonator (SUB = W /2) VCC = 3.0 V 32-kHz crystal resonator (SUB = W /8)
1
mA
1, 2 Reference value
Rev. 6.00 Sep 12, 2006 page 412 of 526 REJ09B0326-0600
Section 13 Electrical Characteristics Applicable Pins Min VCC Values Typ 5 Max 10 Unit Test Condition A VCC = 3.0 V 32-kHz crystal resonator (SUB = W /2) VCC = 3.0 V 32-kHz crystal resonator 32-kHz crystal resonator not used Notes 1, 2
Item
Symbol
Subsleep ISUBSP mode current dissipation Watch mode current dissipation IWATCH
VCC
8
A
1, 2
ISTBY Standby mode current dissipation RAM data retaining voltage VRAM
VCC
5
A
1, 2
VCC
2
V
Notes: 1. Pin states during current measurement are given below. Mode RES Pin Internal State Operates Operates (OSC/128) VCC Only timers operate VCC Only timers operate (OSC/128) VCC VCC VCC Operates VCC System clock oscillator: ceramic or crystal Subclock oscillator: crystal System clock oscillator: ceramic or crystal Subclock oscillator: Pin X1 = VCC 2. Excludes current in pull-up MOS transistors and output buffers. Other Pins Oscillator Pins VCC System clock oscillator: ceramic or crystal Subclock oscillator: Pin X1 = VCC
Active (high-speed) VCC mode Active (mediumspeed) mode Sleep (high-speed) mode Sleep (mediumspeed) mode Subactive mode Subsleep mode Watch mode
Only timers operate, VCC CPU stops Only time base operates, CPU stops CPU and timers both stop VCC
Standby mode
VCC
VCC
Rev. 6.00 Sep 12, 2006 page 413 of 526 REJ09B0326-0600
Section 13 Electrical Characteristics Values Item Allowable output low current (per pin) Allowable output low current (total) Allowable output high current (per pin) Allowable output high current (total) Output pins except port 6 Port 6 Output pins except port 6 Port 6 All output pins All output pins -IOH (-IOH) IOL Symbol IOL Min Typ Max 2 10 40 80 2 30 mA mA mA Unit mA
Rev. 6.00 Sep 12, 2006 page 414 of 526 REJ09B0326-0600
Section 13 Electrical Characteristics
13.4.3
AC Characteristics (HD64F3644, HD64F3643, HD64F3642A)
Table 13.21 lists the control signal timing, and tables 13.22 and 13.23 list the serial interface timing of the HD64F3644, HD64F3643, HD64F3642A. Table 13.21 Control Signal Timing VCC = 4.0 V to 5.5 V, VSS = 0.0 V, Ta = -20C to +75C, unless otherwise specified.
Applicable Pins Values Min Typ 2 tOSC tcyc fW tW tsubcyc X1, X2 X1, X2 Max 16 10 1000 ns 1000 128 25.6 tOSC s kHz s tW VCC = 3.0 V to 5.5 V VCC = 3.0 V to 5.5 V VCC = 3.0 V to 5.5 V *2 VCC = 3.0 V to 5.5 V Unit MHz VCC = 3.0 V to 5.5 V *1 Figure 13.1 Test Condition Reference Figure
Item System clock oscillation frequency OSC clock (OSC) cycle time System clock () cycle time Subclock oscillation frequency Watch clock (W ) cycle time Subclock (SUB) cycle time Instruction cycle time Oscillation stabilization time (crystal resonator) Oscillation stabilization time (ceramic resonator)
Symbol fOSC
OSC1, OSC2 2
OSC1, OSC2 62.5 100 2 2 2
VCC = 3.0 V to 5.5 V *1
32.768 30.5 8 40 60 20 40 2 15 15
tcyc VCC = 3.0 V to 5.5 V tsubcyc ms VCC = 3.0 V to 5.5 V ms VCC = 3.0 V to 5.5 V s ns VCC = 3.0 V to 5.5 V ns VCC = 3.0 V to 5.5 V ns ns VCC = 3.0 V to 5.5 V VCC = 3.0 V to 5.5 V VCC = 3.0 V to 5.5 V Figure 13.1
trc
OSC1, OSC2
trc
OSC1, OSC2 X1, X2 OSC1 OSC1 20 40 20 40
Oscillation stabilization trc time External clock high width External clock low width External clock rise time External clock fall time tCPH tCPL tCPr tCPf
Rev. 6.00 Sep 12, 2006 page 415 of 526 REJ09B0326-0600
Section 13 Electrical Characteristics
Applicable Pins RES Values Min 10 Typ Max Unit tcyc Test Condition Reference Figure
Item Pin RES low width Input pin high level width
Symbol tREL tIH
VCC = 3.0 V to 5.5 V Figure 13.2
IRQ0 to IRQ3, 2 INT0 to INT7, ADTRG, TMIB, TMCIV, TMRIV, FTCI, FTIA, FTIB, FTIC, FTID, TRGV IRQ0 to IRQ3, 2 INT6, INT7, ADTRG, TMIB, TMCIV, TMRIV, FTCI, FTIA, FTIB, FTIC, FTID, TRGV
tcyc VCC = 3.0 V to 5.5 V Figure 13.3 tsubcyc
Input pin low level width
tIL
tcyc VCC = 3.0 V to 5.5 V tsubcyc
Notes: 1. A frequency between 1 MHz to 10 MHz is required when an external clock is input. 2. Selected with SA1 and SA0 of system clock control register 2 (SYSCR2).
Rev. 6.00 Sep 12, 2006 page 416 of 526 REJ09B0326-0600
Section 13 Electrical Characteristics
Table 13.22 Serial Interface (SCI1) Timing VCC = 4.0 V to 5.5 V, VSS = 0.0 V, Ta = -20C to +75C, unless otherwise specified.
Applicable Symbol Pins tScyc tSCKH tSCKL tSCKr SCK1 SCK1 SCK1 SCK1 Values Min 2 0.4 0.4 tSCKf SCK1 SO1 SI1 180 360 tSIH SI1 180 360 Typ Max 60 80 60 80 200 350 ns VCC = 3.0 V to 5.5 V ns VCC = 3.0 V to 5.5 V ns VCC = 3.0 V to 5.5 V ns VCC = 3.0 V to 5.5 V Unit Test Condition tcyc tScyc tScyc ns VCC = 3.0 V to 5.5 V VCC = 3.0 V to 5.5 V VCC = 3.0 V to 5.5 V VCC = 3.0 V to 5.5 V Reference Figure Figure 13.4
Item Input serial clock cycle time Input serial clock high width Input serial clock low width Input serial clock rise time Input serial clock fall time
Serial output data tSOD delay time Serial input data setup time Serial input data hold time tSIS
Rev. 6.00 Sep 12, 2006 page 417 of 526 REJ09B0326-0600
Section 13 Electrical Characteristics
Table 13.23 Serial Interface (SCI3) Timing VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VSS = 0.0 V, Ta = -20C to +75C, unless otherwise specified.
Values Item Input clock cycle Synchronous tSCKW tTXD Symbol Asynchronous tScyc Min 4 6 0.4 Receive data setup time (synchronous) Receive data hold time (synchronous) tRXS Typ Max 0.6 1 1 ns VCC = 4.0 V to 5.5 V ns VCC = 4.0 V to 5.5 V tScyc tcyc VCC = 4.0 V to 5.5 V Figure 13.6 Unit tcyc Reference Test Condition Figure Figure 13.5
Input clock pulse width Transmit data delay time (synchronous)
200.0 400.0
tRXH
200.0 400.0
Rev. 6.00 Sep 12, 2006 page 418 of 526 REJ09B0326-0600
Section 13 Electrical Characteristics
13.4.4
A/D Converter Characteristics
Table 13.24 shows the A/D converter characteristics of the HD64F3644, HD64F3643, and HD64F3642A. Table 13.24 A/D Converter Characteristics VCC = 3.0 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C, unless otherwise specified.
Applicable Symbol Pins Min AVCC 3.0 Values Typ Max 5.5 Test Unit Condition V Referenc e Figure *1
Item
Analog power AVCC supply voltage Analog input voltage AVin
AN0 to AN7 AVSS -0.3 AVCC AVCC
AVSS +0.3 V 1.5 mA A AVCC = 5.0 V *2 Reference value *3
Analog power AIOPE supply AISTOP1 current AISTOP2 Analog input capacitance CAin
150.0
AVCC

5.0 30.0 5.0
A pF k
AN0 to AN7
RAin Allowable signal source impedance Resolution Nonlinearity error Quantization error Absolute accuracy Conversion time
7.75

8 2.0 0.5 2.5 124
bit LSB LSB LSB s
Notes: 1. Set AVCC = VCC when the A/D converter is not used. 2. AISTOP1 is the current in active and sleep modes while the A/D converter is idle. 3. AISTOP2 is the current at reset and in standby, watch, subactive, and subsleep modes while the A/D converter is idle.
Rev. 6.00 Sep 12, 2006 page 419 of 526 REJ09B0326-0600
Section 13 Electrical Characteristics
13.5
Operation Timing
Figures 13.1 to 13.6 show timing diagrams.
t OSC
VIH OSC1 VIL
t CPH t CPr
t CPL t CPf
Figure 13.1 System Clock Input Timing
RES
VIL
tREL
Figure 13.2 RES Low Width Timing
IRQ0 to IRQ3, INT0 to INT7, ADTRG, TMIB, FTIA, FTIB, TMCIV, FTIC, FTID, TMRIV, FTCI, TRGV
VIH VIL
t IL
t IH
Figure 13.3 Input Timing
Rev. 6.00 Sep 12, 2006 page 420 of 526 REJ09B0326-0600
Section 13 Electrical Characteristics
t Scyc
SCK 1
V IH or V OH* V IL or V OL *
t SCKL t SCKf t SOD
t SCKH t SCKr
SO 1
VOH* VOL *
t SIS t SIH
SI 1
Note: * Output timing reference levels Output high: VOH = 2.0 V Output low: VOL = 0.8 V Load conditions are shown in figure 13.7.
Figure 13.4 SCI1 Input/Output Timing
Rev. 6.00 Sep 12, 2006 page 421 of 526 REJ09B0326-0600
Section 13 Electrical Characteristics
t SCKW
SCK 3
t Scyc
Figure 13.5 SCK3 Input Clock Timing
t Scyc
SCK 3
VIH or VOH * VIL or VOL *
t TXD
TXD (transmit data)
VOH VOL
*
*
t RXS
t RXH
RXD (receive data)
Note: * Output timing reference levels Output high: VOH = 2.0 V Output low: VOL = 0.8 V Load conditions are shown in figure 13.7.
Figure 13.6 SCI3 Synchronous Mode Input/Output Timing
Rev. 6.00 Sep 12, 2006 page 422 of 526 REJ09B0326-0600
Section 13 Electrical Characteristics
13.6
Output Load Circuit
VCC
2.4 k
Output pin 30 pF 12 k
Figure 13.7 Output Load Condition
Rev. 6.00 Sep 12, 2006 page 423 of 526 REJ09B0326-0600
Section 13 Electrical Characteristics
Rev. 6.00 Sep 12, 2006 page 424 of 526 REJ09B0326-0600
Appendix A CPU Instruction Set
Appendix A CPU Instruction Set
A.1 Instructions
Operation Notation
Rd8/16 Rs8/16 Rn8/16 CCR N Z V C PC SP #xx: 3/8/16 d: 8/16 @aa: 8/16 + - x / -- General register (destination) (8 or 16 bits) General register (source) (8 or 16 bits) General register (8 or 16 bits) Condition code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data (3, 8, or 16 bits) Displacement (8 or 16 bits) Absolute address (8 or 16 bits) Addition Subtraction Multiplication Division Logical AND Logical OR Exclusive logical OR Move Logical complement
Condition Code Notation
Symbol Modified according to the instruction result * 0 -- Undefined (value not guaranteed) Always cleared to 0 Not affected by the instruction execution result Rev. 6.00 Sep 12, 2006 page 425 of 526 REJ09B0326-0600
Appendix A CPU Instruction Set
Table A.1 lists the H8/300L CPU instruction set. Table A.1 Instruction Set
Addressing Mode/ Instruction Length (Bytes) Condition Code
Operand Size
@aa: 8/16
#xx: 8/16
Mnemonic
Operation
I
HNZVC
MOV.B #xx:8, Rd MOV.B Rs, Rd MOV.B @Rs, Rd MOV.B @(d:16, Rs), Rd MOV.B @Rs+, Rd MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B Rs, @Rd MOV.B Rs, @(d:16, Rd) MOV.B Rs, @-Rd MOV.B Rs, @aa:8 MOV.B Rs, @aa:16 MOV.W #xx:16, Rd MOV.W Rs, Rd MOV.W @Rs, Rd
2 2 2 4 2 2 4 2 4 2 2 4 4 2 2 4 2 4 2 4 2 4 2
---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----

B #xx:8 Rd8 B Rs8 Rd8 B @Rs16 Rd8 B @(d:16, Rs16) Rd8 B @Rs16 Rd8 Rs16+1 Rs16 B @aa:8 Rd8 B @aa:16 Rd8 B Rs8 @Rd16 B Rs8 @(d:16, Rd16) B Rd16-1 Rd16 Rs8 @Rd16 B Rs8 @aa:8 B Rs8 @aa:16 W #xx:16 Rd W Rs16 Rd16 W @Rs16 Rd16 W @Rs16 Rd16 Rs16+2 Rs16 W @aa:16 Rd16 W Rs16 @Rd16 W Rd16-2 Rd16 Rs16 @Rd16 W Rs16 @aa:16 W @SP Rd16 SP+2 SP
0--2 0--2 0--4 0--6 0--6 0--4 0--6 0--4 0--6 0--6 0--4 0--6 0--4 0--2 0--4 0--6 0--6 0--6 0--4 0--6 0--6 0--6 0--6
MOV.W @(d:16, Rs), Rd W @(d:16, Rs16) Rd16 MOV.W @Rs+, Rd MOV.W @aa:16, Rd MOV.W Rs, @Rd
MOV.W Rs, @(d:16, Rd) W Rs16 @(d:16, Rd16) MOV.W Rs, @-Rd MOV.W Rs, @aa:16 POP Rd
Rev. 6.00 Sep 12, 2006 page 426 of 526 REJ09B0326-0600

No. of States
@-Rn/@Rn+
Rn @Rn @(d:16, Rn)
@(d:8, PC) @@aa
Implied
Appendix A CPU Instruction Set
Addressing Mode/ Instruction Length (Bytes) Condition Code
Operand Size
#xx: 8/16 Rn
Mnemonic
Operation
I
HNZVC
PUSH Rs ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W Rs, Rd ADDX.B #xx:8, Rd ADDX.B Rs, Rd ADDS.W #1, Rd ADDS.W #2, Rd INC.B Rd DAA.B Rd SUB.B Rs, Rd SUB.W Rs, Rd SUBX.B #xx:8, Rd SUBX.B Rs, Rd SUBS.W #1, Rd SUBS.W #2, Rd DEC.B Rd DAS.B Rd NEG.B Rd CMP.B #xx:8, Rd CMP.B Rs, Rd CMP.W Rs, Rd MULXU.B Rs, Rd
W SP-2 SP Rs16 @SP B Rd8+#xx:8 Rd8 B Rd8+Rs8 Rd8 W Rd16+Rs16 Rd16 B Rd8+#xx:8 +C Rd8 B Rd8+Rs8 +C Rd8 W Rd16+1 Rd16 W Rd16+2 Rd16 B Rd8+1 Rd8 B Rd8 decimal adjust Rd8 B Rd8-Rs8 Rd8 W Rd16-Rs16 Rd16 B Rd8-#xx:8 -C Rd8 B Rd8-Rs8 -C Rd8 W Rd16-1 Rd16 W Rd16-2 Rd16 B Rd8-1 Rd8 B Rd8 decimal adjust Rd8 B 0-Rd Rd B Rd8-#xx:8 B Rd8-Rs8 W Rd16-Rs16 B Rd8 x Rs8 Rd16 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
2
----

0--6

-- --

-- (1)
-- --
(2) (2)
------------ 2 ------------ 2 ---- --* --

--2
* (3) 2 2 2 2 2
-- (1)
-- --
(2) (2)
------------ 2 ------------ 2 ---- --* -- -- --

--2
*--2 2 2 2 2
-- (1)
-- -- -- -- -- -- 14
Rev. 6.00 Sep 12, 2006 page 427 of 526 REJ09B0326-0600
No. of States
2 2 2 2 2
@-Rn/@Rn+ @aa: 8/16
@(d:16, Rn)
@(d:8, PC)
@@aa Implied
@Rn
Appendix A CPU Instruction Set
Addressing Mode/ Instruction Length (Bytes)
Operand Size @(d:16, Rn) @-Rn/@Rn+ @aa: 8/16
Condition Code
No. of States
#xx: 8/16
Mnemonic
Operation
@(d:8, PC) @@aa
Implied
Rn @Rn
IHNZVC
DIVXU.B Rs, Rd AND.B #xx:8, Rd AND.B Rs, Rd OR.B #xx:8, Rd OR.B Rs, Rd XOR.B #xx:8, Rd XOR.B Rs, Rd NOT.B Rd SHAL.B Rd
B Rd16/Rs8 Rd16 (RdH: remainder, RdL: quotient) B Rd8#xx:8 Rd8 B Rd8Rs8 Rd8 B Rd8#xx:8 Rd8 B Rd8Rs8 Rd8 B Rd8#xx:8 Rd8 B Rd8Rs8 Rd8 B Rd Rd B C b7 b0 0 2 2 2
2
-- -- (5) (6) -- -- 14 ----

0--2 0--2 0--2 0--2 0--2 0--2 0--2

2
---- ----
2
---- ----
2 2 2
---- ---- ----
2
SHAR.B Rd
B b7 b0
C
2
----

0
2
SHLL.B Rd
B
C b7 b0
0
2
----

0
2
SHLR.B Rd
B
0 b7 b0
C
2
----

0
2
ROTXL.B Rd
B
C b7 b0
2
----

0
2
ROTXR.B Rd
B b7 b0 C
2
----

0
2
ROTL.B Rd
B
C b7 b0 C b7 b0
2
----

0
2
ROTR.B Rd
B
2
----

0
2
Rev. 6.00 Sep 12, 2006 page 428 of 526 REJ09B0326-0600
Appendix A CPU Instruction Set
Addressing Mode/ Instruction Length (Bytes) Condition Code
Operand Size
@aa: 8/16
#xx: 8/16 Rn
Mnemonic
Operation
I
HNZVC
BSET #xx:3, Rd BSET #xx:3, @Rd BSET #xx:3, @aa:8 BSET Rn, Rd BSET Rn, @Rd BSET Rn, @aa:8 BCLR #xx:3, Rd BCLR #xx:3, @Rd BCLR #xx:3, @aa:8 BCLR Rn, Rd BCLR Rn, @Rd BCLR Rn, @aa:8 BNOT #xx:3, Rd BNOT #xx:3, @Rd BNOT #xx:3, @aa:8 BNOT Rn, Rd BNOT Rn, @Rd BNOT Rn, @aa:8 BTST #xx:3, Rd BTST #xx:3, @Rd BTST #xx:3, @aa:8 BTST Rn, Rd BTST Rn, @Rd BTST Rn, @aa:8
B (#xx:3 of Rd8) 1 B (#xx:3 of @Rd16) 1 B (#xx:3 of @aa:8) 1 B (Rn8 of Rd8) 1 B (Rn8 of @Rd16) 1 B (Rn8 of @aa:8) 1 B (#xx:3 of Rd8) 0 B (#xx:3 of @Rd16) 0 B (#xx:3 of @aa:8) 0 B (Rn8 of Rd8) 0 B (Rn8 of @Rd16) 0 B (Rn8 of @aa:8) 0 B (#xx:3 of Rd8) (#xx:3 of Rd8) B (#xx:3 of @Rd16) (#xx:3 of @Rd16) B (#xx:3 of @aa:8) (#xx:3 of @aa:8) B (Rn8 of Rd8) (Rn8 of Rd8) B (Rn8 of @Rd16) (Rn8 of @Rd16) B (Rn8 of @aa:8) (Rn8 of @aa:8) B (#xx:3 of Rd8) Z B (#xx:3 of @Rd16) Z B (#xx:3 of @aa:8) Z B (Rn8 of Rd8) Z B (Rn8 of @Rd16) Z B (Rn8 of @aa:8) Z
2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4
------------ 2 ------------ 8 ------------ 8 ------------ 2 ------------ 8 ------------ 8 ------------ 2 ------------ 8 ------------ 8 ------------ 2 ------------ 8 ------------ 8 ------------ 2 ------------ 8 ------------ 8 ------------ 2 ------------ 8 ------------ 8 ------ ------ ------ ------ ------ ------
---- 2 ---- 6 ---- 6 ---- 2 ---- 6 ---- 6
Rev. 6.00 Sep 12, 2006 page 429 of 526 REJ09B0326-0600
No. of States
@(d:16, Rn) @-Rn/@Rn+
@(d:8, PC)
@@aa Implied
@Rn
Appendix A CPU Instruction Set
Addressing Mode/ Instruction Length (Bytes) Condition Code
Operand Size
@aa: 8/16
#xx: 8/16
Mnemonic
Operation
I
HNZVC
BLD #xx:3, Rd BLD #xx:3, @Rd BLD #xx:3, @aa:8 BILD #xx:3, Rd BILD #xx:3, @Rd BILD #xx:3, @aa:8 BST #xx:3, Rd BST #xx:3, @Rd BST #xx:3, @aa:8 BIST #xx:3, Rd BIST #xx:3, @Rd BIST #xx:3, @aa:8 BAND #xx:3, Rd BAND #xx:3, @Rd BAND #xx:3, @aa:8 BIAND #xx:3, Rd BIAND #xx:3, @Rd BIAND #xx:3, @aa:8 BOR #xx:3, Rd BOR #xx:3, @Rd BOR #xx:3, @aa:8 BIOR #xx:3, Rd BIOR #xx:3, @Rd BIOR #xx:3, @aa:8 BXOR #xx:3, Rd BXOR #xx:3, @Rd BXOR #xx:3, @aa:8 BIXOR #xx:3, Rd
2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2
---------- ---------- ---------- ---------- ---------- ----------

B (#xx:3 of Rd8) C B (#xx:3 of @Rd16) C B (#xx:3 of @aa:8) C B (#xx:3 of Rd8) C B (#xx:3 of @Rd16) C B (#xx:3 of @aa:8) C B C (#xx:3 of Rd8) B C (#xx:3 of @Rd16) B C (#xx:3 of @aa:8) B C (#xx:3 of Rd8) B C (#xx:3 of @Rd16) B C (#xx:3 of @aa:8) B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C B C(#xx:3 of Rd8) C
------------ 2 ------------ 8 ------------ 8 ------------ 2 ------------ 8 ------------ 8 ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6 2
Rev. 6.00 Sep 12, 2006 page 430 of 526 REJ09B0326-0600
No. of States
2 6 6 2 6 6
@(d:16, Rn) @-Rn/@Rn+
@(d:8, PC) @@aa
Implied
Rn @Rn
Appendix A CPU Instruction Set
Addressing Mode/ Instruction Length (Bytes)
Operand Size @-Rn/@Rn+ @aa: 8/16 @(d:16, Rn)
Condition Code
No. of States
@@aa Implied
@Rn
Branching Condition
#xx: 8/16 Rn
Mnemonic
Operation
@(d:8, PC)
IHNZVC ----------
BIXOR #xx:3, @Rd BIXOR #xx:3, @aa:8 BRA d:8 (BT d:8) BRN d:8 (BF d:8) BHI d:8 BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 BMI d:8 BGE d:8 BLT d:8 BGT d:8 BLE d:8 JMP @Rn JMP @aa:16 JMP @@aa:8 BSR d:8
B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C -- PC PC+d:8 -- PC PC+2 -- If condition -- is true -- then -- PC PC+d:8 -- else next; -- -- -- -- -- -- -- -- -- -- PC Rn16 -- PC aa:16 -- PC @aa:8 -- SP-2 SP PC @SP PC PC+d:8 -- SP-2 SP PC @SP PC Rn16 -- SP-2 SP PC @SP PC aa:16 CZ=0 CZ=1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV = 0 NV = 1 Z (NV) = 0 Z (NV) = 1
4 4 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 4 2 2
6 6
----------
------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 6 ------------ 8 ------------ 6
JSR @Rn
2
------------ 6
JSR @aa:16
4
------------ 8
Rev. 6.00 Sep 12, 2006 page 431 of 526 REJ09B0326-0600
Appendix A CPU Instruction Set
Addressing Mode/ Instruction Length (Bytes) Condition Code
Operand Size
@aa: 8/16
#xx: 8/16
Mnemonic
Operation
I
HNZVC
JSR @@aa:8
-- SP-2 SP PC @SP PC @aa:8 -- PC @SP SP+2 SP -- CCR @SP SP+2 SP PC @SP SP+2 SP -- Transit to sleep mode. B #xx:8 CCR B Rs8 CCR B CCR Rd8 B CCR#xx:8 CCR B CCR#xx:8 CCR B CCR#xx:8 CCR -- PC PC+2 -- if R4L0 Repeat @R5 @R6 R5+1 R5 R6+1 R6 R4L-1 R4L Until R4L=0 else next; 2 2 2 2 2 2
2
------------ 8
RTS RTE
2 ------------ 8

2
10
SLEEP LDC #xx:8, CCR LDC Rs, CCR STC CCR, Rd ANDC #xx:8, CCR ORC #xx:8, CCR XORC #xx:8, CCR NOP EEPMOV
2 ------------ 2

------------ 2

2 ------------ 2 4 ------------ 4
Notes: (1) Set to 1 when there is a carry or borrow from bit 11; otherwise cleared to 0. (2) If the result is zero, the previous value of the flag is retained; otherwise the flag is cleared to 0. (3) Set to 1 if decimal adjustment produces a carry; otherwise retains value prior to arithmetic operation. (4) The number of states required for execution is 4n + 9 (n = value of R4L). (5) Set to 1 if the divisor is negative; otherwise cleared to 0. (6) Set to 1 if the divisor is zero; otherwise cleared to 0.
Rev. 6.00 Sep 12, 2006 page 432 of 526 REJ09B0326-0600
No. of States
2 2 2 2 2
@(d:16, Rn) @-Rn/@Rn+
@(d:8, PC) @@aa
Implied
Rn @Rn
Appendix A CPU Instruction Set
A.2
Operation Code Map
Table A.2 is an operation code map. It shows the operation codes contained in the first byte of the instruction code (bits 15 to 8 of the first instruction word). Instruction when first bit of byte 2 (bit 7 of first instruction word) is 0. Instruction when first bit of byte 2 (bit 7 of first instruction word) is 1.
Rev. 6.00 Sep 12, 2006 page 433 of 526 REJ09B0326-0600
Low 2 STC ADD SUB NEG DEC SUBS CMP SUBX DAS ROTXR OR ROTL ROTR XOR AND NOT LDC ORC XORC ANDC LDC INC ADDS MOV ADDX DAA 3 4 5 6 7 8 9 A B C D E F
High
0
1
Table A.2
0
NOP
SLEEP
SHLL
SHLR
ROTXL
1
SHAL
SHAR
2 MOV
3 BHI RTS BST BCLR BOR MOV BIOR ADD ADDX CMP SUBX OR XOR AND MOV BIXOR BIAND BILD BXOR BAND BTST BIST BLD EEPMOV Bit-manipulation instructions MOV * BSR RTE JMP BLS BCC BCS BEQ BVC BVS BNE BPL BMI BGE BLT BGT JSR BLE
4
BRA
BRN
Appendix A CPU Instruction Set
Operation Code Map
5
MULXU
DIVXU
6
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BSET
BNOT
7
8
9
A
B
C
D
E
F
Note: * The PUSH and POP instructions are identical in machine language to MOV instructions.
Appendix A CPU Instruction Set
A.3
Number of Execution States
The tables here can be used to calculate the number of states required for instruction execution. Table A.3 indicates the number of states required for each cycle (instruction fetch, branch address read, stack operation, byte data access, word data access, internal operation). Table A.4 indicates the number of cycles of each type occurring in each instruction. The total number of states required for execution of an instruction can be calculated from these two tables as follows:
Execution states = I x SI + J x SJ + K x SK + L x SL + M x SM + N x SN
Examples: When instruction is fetched from on-chip ROM, and an on-chip RAM is accessed. BSET #0, @FF00 From table A.4: I = L = 2, J = K = M = N= 0 From table A.3: SI = 2, SL = 2 Number of states required for execution = 2 x 2 + 2 x 2 = 8 When instruction is fetched from on-chip ROM, branch address is read from on-chip ROM, and on-chip RAM is used for stack area. JSR @@ 30 From table A.4: I = 2, J = K = 1, From table A.3: SI = SJ = SK = 2 Number of states required for execution = 2 x 2 + 1 x 2+ 1 x 2 = 8
L=M=N=0
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Appendix A CPU Instruction Set
Table A.3
Number of Cycles in Each Instruction
Access Location On-Chip Memory SI SJ SK SL SM SN 1 2 or 3* -- 2 On-Chip Peripheral Module --
Execution Status (Instruction Cycle) Instruction fetch Branch address read Stack operation Byte data access Word data access Internal operation Note: *
Depends on which on-chip module is accessed. See section 2.9.1, Notes on Data Access for details.
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Appendix A CPU Instruction Set
Table A.4
Number of Cycles in Each Instruction
Instruction Branch Stack Byte Data Fetch Addr. Read Operation Access I J K L 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 2 1 2 2 1 1 Word Data Internal Access Operation M N
Instruction Mnemonic ADD ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W Rs, Rd ADDS ADDX AND ANDC BAND ADDS.W #1, Rd ADDS.W #2, Rd ADDX.B #xx:8, Rd ADDX.B Rs, Rd AND.B #xx:8, Rd AND.B Rs, Rd ANDC #xx:8, CCR BAND #xx:3, Rd BAND #xx:3, @Rd BAND #xx:3, @aa:8 Bcc BRA d:8 (BT d:8) BRN d:8 (BF d:8) BHI d:8 BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 BMI d:8 BGE d:8 BLT d:8 BGT d:8 BLE d:8 BCLR BCLR #xx:3, Rd BCLR #xx:3, @Rd BCLR #xx:3, @aa:8 BCLR Rn, Rd
Rev. 6.00 Sep 12, 2006 page 437 of 526 REJ09B0326-0600
Appendix A CPU Instruction Set
Instruction Branch Stack Byte Data Fetch Addr. Read Operation Access I J K L 2 2 1 2 1 2 2 1 2 2 1 2 2 1 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 2 2 1 1 2 2 2 2 1 1 1 1 2 2 1 1 1 1 1 1 2 2 Word Data Internal Access Operation M N
Instruction Mnemonic BCLR BIAND BCLR Rn, @Rd BCLR Rn, @aa:8 BIAND #xx:3, Rd BIAND #xx:3, @Rd BILD BILD #xx:3, Rd BILD #xx:3, @Rd BILD #xx:3, @aa:8 BIOR BIOR #xx:3, Rd BIOR #xx:3, @Rd BIOR #xx:3, @aa:8 BIST BIST #xx:3, Rd BIST #xx:3, @Rd BIST #xx:3, @aa:8 BIXOR BIXOR #xx:3, Rd BIXOR #xx:3, @Rd BLD BLD #xx:3, Rd BLD #xx:3, @Rd BLD #xx:3, @aa:8 BNOT BNOT #xx:3, Rd BNOT #xx:3, @Rd BNOT #xx:3, @aa:8 BNOT Rn, Rd BNOT Rn, @Rd BNOT Rn, @aa:8 BOR BOR #xx:3, Rd BOR #xx:3, @Rd BOR #xx:3, @aa:8 BSET BSET #xx:3, Rd BSET #xx:3, @Rd BSET #xx:3, @aa:8 BSET Rn, Rd BSET Rn, @Rd
BIAND #xx:3, @aa:8 2
BIXOR #xx:3, @aa:8 2
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Appendix A CPU Instruction Set
Instruction Branch Stack Byte Data Fetch Addr. Read Operation Access I J K L 2 2 1 2 2 1 2 2 1 2 2 1 2 1 1 1 1 1 1 1 2 1 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 2 2 2 2n+2* 12 1 1 1 1 1 1 1 2 2 1 2 Word Data Internal Access Operation M N
Instruction Mnemonic BSET BSR BST BSET Rn, @aa:8 BSR d:8 BST #xx:3, Rd BST #xx:3, @Rd BST #xx:3, @aa:8 BTST BTST #xx:3, Rd BTST #xx:3, @Rd BTST #xx:3, @aa:8 BTST Rn, Rd BTST Rn, @Rd BTST Rn, @aa:8 BXOR BXOR #xx:3, Rd BXOR #xx:3, @Rd CMP CMP. B #xx:8, Rd CMP. B Rs, Rd CMP.W Rs, Rd DAA DAS DEC DIVXU EEPMOV INC JMP DAA.B Rd DAS.B Rd DEC.B Rd DIVXU.B Rs, Rd EEPMOV INC.B Rd JMP @Rn JMP @aa:16 JMP @@aa:8 JSR JSR @Rn JSR @aa:16 JSR @@aa:8 LDC MOV LDC #xx:8, CCR LDC Rs, CCR MOV.B #xx:8, Rd MOV.B Rs, Rd
BXOR #xx:3, @aa:8 2
Rev. 6.00 Sep 12, 2006 page 439 of 526 REJ09B0326-0600
Appendix A CPU Instruction Set
Instruction Branch Stack Byte Data Fetch Addr. Read Operation Access I J K L 1 1 1 1 1 1 1 1 1 1 1 2 2 Word Data Internal Access Operation M N
Instruction Mnemonic MOV MOV.B @Rs, Rd
MOV.B @(d:16, Rs), 2 Rd MOV.B @Rs+, Rd MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B Rs, @Rd MOV.B Rs, @(d:16, Rd) MOV.B Rs, @-Rd MOV.B Rs, @aa:8 MOV.B Rs, @aa:16 MOV.W #xx:16, Rd MOV.W Rs, Rd MOV.W @Rs, Rd 1 1 2 1 2 1 1 2 2 1 1
1 1 1 1 1 1 1 1 12 2 2
MOV.W @(d:16, Rs), 2 Rd MOV.W @Rs+, Rd MOV.W Rs, @Rd MOV.W Rs, @-Rd MULXU NEG NOP NOT OR ORC ROTL ROTR ROTXL ROTXR MULXU.B Rs, Rd NEG.B Rd NOP NOT.B Rd OR.B #xx:8, Rd OR.B Rs, Rd ORC #xx:8, CCR ROTL.B Rd ROTR.B Rd ROTXL.B Rd ROTXR.B Rd 1 1 1 1 1 1 1 1 1 1 1 1 1 1 MOV.W @aa:16, Rd 2 MOV.W Rs, @(d:16d) 2 MOV.W Rs, @aa:16 2
Rev. 6.00 Sep 12, 2006 page 440 of 526 REJ09B0326-0600
Appendix A CPU Instruction Set
Instruction Branch Stack Byte Data Fetch Addr. Read Operation Access I J K L 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 1 Word Data Internal Access Operation M N 2 2
Instruction Mnemonic RTE RTS SHAL SHAR SHLL SHLR SLEEP STC SUB SUBS POP PUSH SUBX XOR XORC RTE RTS SHAL.B Rd SHAR.B Rd SHLL.B Rd SHLR.B Rd SLEEP STC CCR, Rd SUB.B Rs, Rd SUB.W Rs, Rd SUBS.W #1, Rd SUBS.W #2, Rd POP Rd PUSH Rs SUBX.B #xx:8, Rd SUBX.B Rs, Rd XOR.B #xx:8, Rd XOR.B Rs, Rd XORC #xx:8, CCR
Note: n: Initial value in R4L. The source and destination operands are accessed n + 1 times each.
Rev. 6.00 Sep 12, 2006 page 441 of 526 REJ09B0326-0600
Appendix B Internal I/O Registers
Appendix B Internal I/O Registers
B.1 Addresses
Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name
Register Address Name Bit 7 H'F740 H'F741 H'F742 H'F743 H'F744 H'F770 H'F771 H'F772 H'F773 H'F774 H'F775 H'F776 H'F777 H'F778 H'F779 F'F77A F'F77B H'F77C H'F77D H'F77E H'F77F H'FF80 H'FF81 H'FF82 H'FF83 EBR1 EBR2 -- SB7 TIER TCSRX FRCH FRCL
OCRAH/ OCRBH OCRAL/ OCRBL
ICIAE ICFA FRCH7 FRCL7
ICIBE ICFB FRCH6 FRCL6
ICICE ICFC FRCH5 FRCL5
ICIDE ICFD FRCH4 FRCL4
OCIAE OCFA FRCH3 FRCL3
OCIBE OCFB FRCH2 FRCL2
OVIE OVF FRCH1 FRCL1
-- CCLRA FRCH0 FRCL0
Timer X
OCRAH7/ OCRAH6/ OCRAH5/ OCRAH4/ OCRAH3/ OCRAH2/ OCRAH1/ OCRAH0/ OCRBH7 OCRBH6 OCRBH5 OCRBH4 OCRBH3 OCRBH2 OCRBH1 OCRBH0 OCRAL7/ OCRAL6/ OCRAL5/ OCRAL4/ OCRAL3/ OCRAL2/ OCRAL1/ OCRAL0/ OCRBL7 OCRBL6 OCRBL5 OCRBL4 OCRBL3 OCRBL2 OCRBL1 OCRBL0
TCRX TOCR ICRAH ICRAL ICRBH ICRBL ICRCH ICRCL ICRDH ICRDL FLMCR
IEDGA --
IEDGB --
IEDGC --
IEDGD OCRS
BUFEA OEA
BUFEB OEB
CKS1 OLVLA
CKS0 OLVLB
ICRAH7 ICRAH6 ICRAH5 ICRAH4 ICRAH3 ICRAH2 ICRAH1 ICRAH0 ICRAL7 ICRAL6 ICRAL5 ICRAL4 ICRAL3 ICRAL2 ICRAL1 ICRAL0 ICRBH7 ICRBH6 ICRBH5 ICRBH4 ICRBH3 ICRBH2 ICRBH1 ICRBH0 ICRBL7 ICRBL6 ICRBL5 ICRBL4 ICRBL3 ICRBL2 ICRBL1 ICRBL0 ICRCH7 ICRCH6 ICRCH5 ICRCH4 ICRCH3 ICRCH2 ICRCH1 ICRCH0 ICRCL7 ICRCL6 ICRCL5 ICRCL4 ICRCL3 ICRCL2 ICRCL1 ICRCL0 ICRDH7 ICRDH6 ICRDH5 ICRDH4 ICRDH3 ICRDH2 ICRDH1 ICRDH0 ICRDL7 ICRDL6 ICRDL5 ICRDL4 ICRDL3 ICRDL2 ICRDL1 ICRDL0 VPP -- -- -- EV PV E P Flash memory (flash memory version only)
-- SB6
-- SB5
-- SB4
LB3 SB3
LB2 SB2
LB1 SB1
LB0 SB0
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Appendix B Internal I/O Registers
Register Address Name Bit 7 H'FFA0 H'FFA1 H'FFA2 H'FFA3 H'FFA4 H'FFA5 H'FFA6 H'FFA7 H'FFA8 H'FFA9 H'FFAA H'FFAB SMR BRR SCR3 TDR COM BRR7 TIE TDR7 TDRE RDR7 CHR BRR6 RIE TDR6 RDRF RDR6 PE BRR5 TE TDR5 OER RDR5 PM BRR4 RE TDR4 FER RDR4 STOP BRR3 MPIE TDR3 PER RDR3 MP BRR2 TEIE TDR2 TEND RDR2 CKS1 BRR1 CKE1 TDR1 MPBR RDR1 CKS0 BRR0 CKE0 TDR0 MPBT RDR0 SCI3 SCR1 SCSR1 SDRU SDRL SNC1 -- SDRU7 SDRL7 Bit Names Bit 6 SNC0 SOL SDRU6 SDRL6 Bit 5 ORER SDRU5 SDRL5 Bit 4 -- SDRU4 SDRL4 Bit 3 CKS3 -- SDRU3 SDRL3 Bit 2 CKS2 -- SDRU2 SDRL2 Bit 1 CKS1 MTRF SDRU1 SDRL1 Bit 0 CKS0 STF SDRU0 SDRL0 Module Name SCI1
MRKON LTCH
H'FFAC SSR H'FFAD RDR H'FFAE H'FFAF H'FFB0 H'FFB1 H'FFB2 H'FFB3 H'FFB4 H'FFB5 H'FFB6 H'FFB7 H'FFB8 H'FFB9 H'FFBA H'FFBB TCRV0 TCSRV TCORA TCORB TMA TCA TMB1 TCB1/ TLB1
TMA7 TCA7 TMB17 TCB17/ TLB17
TMA6 TCA6 -- TCB16/ TLB16
TMA5 TCA5 -- TCB15/ TLB15
-- TCA4 -- TCB14/ TLB14
TMA3 TCA3 -- TCB13/ TLB13
TMA2 TCA2 TMB12 TCB12/ TLB12
TMA1 TCA1 TMB11 TCB11/ TLB11
TMA0 TCA0 TMB10 TCB10/ TLB10
Timer A Timer B1
CMIEB CMFB
CMIEA CMFA
OVIE OVF
CCLR1 --
CCLR0 OS3
CKS2 OS2
CKS1 OS1
CKS0 OS0
Timer V
TCORA7 TCORA6 TCORA5 TCORA4 TCORA3 TCORA2 TCORA1 TCORA0 TCORB7 TCORB6 TCORB5 TCORB4 TCORB3 TCORB2 TCORB1 TCORB0 TCNTV7 TCNTV6 TCNTV5 TCNTV4 TCNTV3 TCNTV2 TCNTV1 TCNTV0 -- -- -- TVEG1 TVEG0 TRGE -- ICKS0
H'FFBC TCNTV H'FFBD TCRV1
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Appendix B Internal I/O Registers
Register Address Name Bit 7 H'FFBE H'FFBF H'FFC0 H'FFC1 H'FFC2 H'FFC3 H'FFC4 H'FFC5 H'FFC6 H'FFC7 H'FFC8 H'FFC9 H'FFCA H'FFCB H'FFCC H'FFCD H'FFCE H'FFCF H'FFD0 H'FFD1 H'FFD2 H'FFD3 H'FFD4 H'FFD5 H'FFD6 H'FFD7 H'FFD8 H'FFD9 PDR5 PDR6 P57 P67 P77 P87 -- PB7 P56 P66 P76 P86 -- PB6 P55 P65 P75 P85 -- PB5 P54 P64 P74 P84 P94 PB4 P53 P63 P73 P83 P93 PB3 P52 P62 -- P82 P92 PB2 P51 P61 -- P81 P91 PB1 P50 P60 -- P80 P90 PB0 PDR1 PDR2 PDR3 P17 -- -- P16 -- -- P15 -- -- P14 -- -- -- -- -- -- P22 P32 -- P21 P31 P10 P20 P30 I/O ports PWCR -- -- -- PWDRU -- -- -- -- -- -- PWCR0 14-bit PWDRU5 PWDRU4 PWDRU3 PWDRU2 PWDRU1 PWDRU0 PWM AMR ADRR ADSR CKS ADR7 ADSF TRGE ADR6 -- -- ADR5 -- -- ADR4 -- CH3 ADR3 -- CH2 ADR2 -- CH1 ADR1 -- CH0 ADR0 -- A/D converter TCSRW B6WI TCW TCW7 Bit Names Bit 6 TCWE TCW6 Bit 5 B4WI TCW5 Bit 4 TCW4 Bit 3 TCW3 Bit 2 WDON TCW2 Bit 1 B0WI TCW1 Bit 0 WRST TCW0 Module Name Watchdog timer
TCSRWE B2WI
PWDRL PWDRL7 PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0
H'FFDA PDR7 H'FFDB PDR8 H'FFDC PDR9 H'FFDD PDRB H'FFDE H'FFDF
Rev. 6.00 Sep 12, 2006 page 444 of 526 REJ09B0326-0600
Appendix B Internal I/O Registers
Register Address Name Bit 7 H'FFE0 H'FFE1 H'FFE2 H'FFE3 H'FFE4 H'FFE5 H'FFE6 H'FFE7 H'FFE8 H'FFE9 H'FFEA H'FFEB PCR5 PCR6 PCR7 PCR8 PCR57 PCR67 PCR77 PCR87 -- -- PCR56 PCR66 PCR76 PCR86 -- -- STS2 -- -- INTEG6 IENAD PCR55 PCR65 PCR75 PCR85 -- -- STS1 -- -- INTEG5 -- -- -- -- INTF5 PCR54 PCR64 PCR74 PCR84 PCR94 -- STS0 NESEL -- INTEG4 -- IENS1 -- IRRS1 INTF4 PCR53 PCR63 PCR73 PCR83 PCR93 -- LSON DTON IEG3 INTEG3 IEN3 -- IRRI3 -- INTF3 PCR52 PCR62 -- PCR82 PCR92 -- PCR51 PCR61 -- PCR81 PCR91 -- PCR50 PCR60 -- PCR80 PCR90 PUCR10 PCR1 PCR2 PCR3 PCR17 -- -- PCR16 -- -- PCR15 -- -- PCR14 -- -- -- -- -- -- PCR22 PCR32 -- PCR21 PCR31 PCR10 PCR20 PCR30 Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name I/O ports
H'FFEC PCR9 H'FFED PUCR1 H'FFEE H'FFEF H'FFF0 H'FFF1 H'FFF2 H'FFF3 H'FFF4 H'FFF5 H'FFF6 H'FFF7 H'FFF8 H'FFF9 H'FFFA H'FFFB H'FFFC H'FFFD H'FFFE H'FFFF PMR7 PMR1 PMR3 PUCR3 PUCR5
PUCR17 PUCR16 PUCR15 PUCR14 --
PUCR32 PUCR31 PUCR30 -- MSON IEG2 INTEG2 IEN2 -- IRRI2 -- INTF2 MA1 SA1 IEG1 INTEG1 IEN1 -- IRRI1 -- INTF1 MA0 SA0 IEG0 INTEG0 IEN0 -- IRRI0 -- INTF0 System control
PUCR57 PUCR56 PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50
SYSCR1 SSBY SYSCR2 -- IEGR1 IEGR2 IENR1 IENR2 IENR3 IRR1 IRR2 IRR3 -- INTEG7 IENDT
IENTB1 IENTA
INTEN7 INTEN6 INTEN5 INTEN4 INTEN3 INTEN2 INTEN1 INTEN0 IRRTB1 IRRTA IRRDT INTF7 IRRAD INTF6
IRQ3 -- --
IRQ2 -- --
IRQ1 -- --
PWM -- --
-- -- --
-- SO1 TXD
-- SI1 --
TMOW SCK1 POF1
I/O ports
I/O ports
Legend: SCI1: Serial communication interface 1
Rev. 6.00 Sep 12, 2006 page 445 of 526 REJ09B0326-0600
Appendix B Internal I/O Registers
B.2
Functions
Register name Address to which the register is mapped Name of on-chip supporting module
Timer C
Register acronym
TMC--Timer mode register C
H'B4
Bit numbers
Bit 7 TMC7 Initial value Read/Write 0 R/W 6 TMC6 0 R/W 5 TMC5 0 R/W 4 -- 1 -- 3 -- 1 -- 2 TMC2 0 R/W 1 TMC1 0 R/W 0 TMC0 0 R/W
Initial bit values
Names of the bits. Dashes (--) indicate reserved bits.
Possible types of access R W Read only Write only
R/W Read and write
Clock select 0 0 0 Internal clock: /8192 1 Internal clock: /2048 1 0 Internal clock: /512 1 Internal clock: /64 1 0 0 Internal clock: /16 1 Internal clock: /4 1 0 Internal clock: W/4 1 External event (TMIC): Rising or falling edge Counter up/down control 0 0 TCC is an up-counter 1 TCC is a down-counter 1 * TCC up/down control is determined by input at pin UD. TCC is a down-counter if the UD input is high, and an up-counter if the UD input is low. Auto-reload function select 0 Interval timer function selected 1 Auto-reload function selected * Don't care
Full name of bit
Descriptions of bit settings
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Appendix B Internal I/O Registers
TIER--Timer interrupt enable register
Bit Initial value Read/Write 7 ICIAE 0 R/W 6 ICIBE 0 R/W 5 ICICE 0 R/W 4 ICIDE 0 R/W 3
H'F770
2 OCIBE 0 R/W 1 OVIE 0 R/W
Timer X
0 -- 1 --
OCIAE 0 R/W
Timer overflow interrupt enable 0 Interrupt request (FOVI) by OVF is disabled 1 Interrupt request (FOVI) by OVF is enabled Output compare interrupt B enable 0 Interrupt request (OCIB) by OCFB is disabled 1 Interrupt request (OCIB) by OCFB is enabled Output compare interrupt A enable 0 Interrupt request (OCIA) by OCFA is disabled 1 Interrupt request (OCIA) by OCFA is enabled Input capture interrupt D enable 0 Interrupt request (ICID) by ICFD is disabled 1 Interrupt request (ICID) by ICFD is enabled Input capture interrupt C enable 0 Interrupt request (ICIC) by ICFC is disabled 1 Interrupt request (ICIC) by ICFC is enabled Input capture interrupt B enable 0 Interrupt request (ICIB) by ICFB is disabled 1 Interrupt request (ICIB) by ICFB is enabled Input capture interrupt A enable 0 Interrupt request (ICIA) by ICFA is disabled 1 Interrupt request (ICIA) by ICFA is enabled
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Appendix B Internal I/O Registers
TCSRX--Timer control/status register X
Bit Initial value Read/Write 7 ICFA 0 R/(W)* 6 ICFB 0 R/(W)* 5 ICFC 0 R/(W)* 4 ICFD 0 R/(W)* 3 OCFA 0 R/(W)*
H'F771
2 OCFB 0 R/(W)* 1 OVF 0 R/(W)* 0
Timer X
CCLRA 0 R/W
Counter clear A 0 FRC is not cleared by compare match A 1 FRC is cleared by compare match A Timer overflow 0 [Clearing condition] After reading OVF = 1, cleared by writing 0 to OVF 1 [Setting condition] Set when the FRC value goes from H'FFFF to H'0000 Output compare flag B 0 [Clearing condition] After reading OCFB = 1, cleared by writing 0 to OCFB 1 [Setting condition] Set when FRC matches OCRB Output compare flag A 0 [Clearing condition] After reading OCFA = 1, cleared by writing 0 to OCFA 1 [Setting condition] Set when FRC matches OCRA Input capture flag D 0 [Clearing condition] After reading ICFD = 1, cleared by writing 0 to ICFD 1 [Setting condition] Set by input capture signal Input capture flag C 0 [Clearing condition] After reading ICFC = 1, cleared by writing 0 to ICFC 1 [Setting condition] Set by input capture signal Input capture flag B 0 [Clearing condition] After reading ICFB = 1, cleared by writing 0 to ICFB 1 [Setting condition] When the value of FRC is transferred to ICRB by the input capture signal Input capture flag A 0 [Clearing condition] After reading ICFA = 1, cleared by writing 0 to ICFA 1 [Setting condition] When the value of FRC is transferred to ICRA by the input capture signal
Note: * Only a write of 0 for flag clearing is possible.
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Appendix B Internal I/O Registers
FRCH--Free-running counter H
Bit Initial value Read/Write 7 FRCH7 0 R/W 6 FRCH6 0 R/W 5 FRCH5 0 R/W 4 FRCH4 0 R/W 3
H'F772
2 FRCH2 0 R/W 1 FRCH1 0 R/W
Timer X
0 FRCH0 0 R/W
FRCH3 0 R/W
Count value
FRCL--Free-running counter L
Bit Initial value Read/Write 7 FRCL7 0 R/W 6 FRCL6 0 R/W 5 FRCL5 0 R/W 4 FRCL4 0 R/W 3
H'F773
2 FRCL2 0 R/W 1 FRCL1 0 R/W
Timer X
0 FRCL0 0 R/W
FRCL3 0 R/W
Count value
OCRAH--Output compare register AH
Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W
H'F774
2 1 R/W 1 1 R/W
Timer X
0 1 R/W
OCRAH7 OCRAH6 OCRAH5 OCRAH4 OCRAH3 OCRAH2 OCRAH1 OCRAH0
OCRBH--Output compare register BH
Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W
H'F774
2 1 R/W 1 1 R/W
Timer X
0 1 R/W
OCRBH7 OCRBH6 OCRBH5 OCRBH4 OCRBH3 OCRBH2 OCRBH1 OCRBH0
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Appendix B Internal I/O Registers
OCRAL--Output compare register AL
Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W
H'F775
2 1 R/W 1 1 R/W
Timer X
0 1 R/W
OCRAL7 OCRAL6 OCRAL5 OCRAL4 OCRAL3 OCRAL2 OCRAL1 OCRAL0
OCRBL--Output compare register BL
Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W
H'F775
2 1 R/W 1 1 R/W
Timer X
0 1 R/W
OCRBL7 OCRBL6 OCRBL5 OCRBL4 OCRBL3 OCRBL2 OCRBL1 OCRBL0
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Appendix B Internal I/O Registers
TCRX--Timer control register X
Bit Initial value Read/Write 7 IEDGA 0 R/W 6 IEDGB 0 R/W 5 IEDGC 0 R/W 4 IEDGD 0 R/W 3
H'F776
2 BUFEB 0 R/W 1 CKS1 0 R/W
Timer X
0 CKS0 0 R/W
BUFEA 0 R/W
Clock select 0 0 Internal clock: /2 1 Internal clock: /8 1 0 Internal clock: /32 1 Internal clock: rising edge Buffer enable B 0 ICRD is not used as a buffer register for ICRB 1 ICRD is used as a buffer register for OCRB Buffer enable A 0 ICRC is not used as a buffer register for ICRA 1 ICRC is used as a buffer register for OCRA Input edge select D 0 Rising edge of input D is captured 1 Falling edge of input D is captured Input edge select C 0 Rising edge of input C is captured 1 Falling edge of input C is captured Input edge select B 0 Rising edge of input B is captured 1 Falling edge of input B is captured Input edge select A 0 Rising edge of input A is captured 1 Falling edge of input A is captured
Rev. 6.00 Sep 12, 2006 page 451 of 526 REJ09B0326-0600
Appendix B Internal I/O Registers
TOCR--Timer Output compare control register
Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 OCRS 0 R/W 3 OEA 0 R/W
H'F777
2 OEB 0 R/W 1 OLVLA 0 R/W
Timer X
0 OLVLB 0 R/W
Output level B 0 Low level 1 High level Output level A 0 Low level 1 High level Output enable B 0 Output compare B output is disabled 1 Output compare B output is enabled Output enable A 0 Output compare A output is disabled 1 Output compare A output is enabled Output compare register select 0 OCRA is selected 1 OCRB is selected
Rev. 6.00 Sep 12, 2006 page 452 of 526 REJ09B0326-0600
Appendix B Internal I/O Registers
ICRAH--Input capture register AH
Bit Initial value Read/Write 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R
H'F778
2 0 R 1 0 R
Timer X
0 0 R
ICRAH7 ICRAH6 ICRAH5 ICRAH4 ICRAH3 ICRAH2 ICRAH1 ICRAH0
ICRAL--Input capture register AL
Bit Initial value Read/Write 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R
H'F779
2 0 R 1 0 R
Timer X
0 0 R
ICRAL7 ICRAL6
ICRAL5 ICRAL4 ICRAL3 ICRAL2
ICRAL1 ICRAL0
ICRBH--Input capture register BH
Bit Initial value Read/Write 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R
H'F77A
2 0 R 1 0 R
Timer X
0 0 R
ICRBH7 ICRBH6 ICRBH5 ICRBH4 ICRBH3 ICRBH2 ICRBH1 ICRBH0
ICRBL--Input capture register BL
Bit Initial value Read/Write 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R
H'F77B
2 0 R 1 0 R
Timer X
0 0 R
ICRBL7 ICRBL6
ICRBL5 ICRBL4 ICRBL3 ICRBL2
ICRBL1 ICRBL0
Rev. 6.00 Sep 12, 2006 page 453 of 526 REJ09B0326-0600
Appendix B Internal I/O Registers
FLMCR--Flash memory control register
H'FF80
Flash memory (Flash memory version only)
2 PV 0 R/W 1 E 0 R/W 0 P 0 R/W
Bit Initial value Read/Write
7 VPP 0 R
6 -- 0 --
5 -- 0 --
4 -- 0 --
3 EV 0 R/W
Program mode 0 Exit from program mode 1 Transition to program mode Erase mode 0 Exit from erase mode 1 Transition to erase mode Program-verify mode 0 Exit from program-verify mode 1 Transition to program-verify mode Erase-verify mode 0 Exit from erase-verify mode 1 Transition to erase-verify mode Programming power 0 12 V is not applied to the FVPP pin 1 12 V is applied to the FVPP pin
Rev. 6.00 Sep 12, 2006 page 454 of 526 REJ09B0326-0600
Appendix B Internal I/O Registers
EBR1--Erase block register 1
H'FF82
Flash memory (Flash memory version only)
2 LB2 0 R/W 1 LB1 0 R/W 0 LB0 0 R/W
Bit Initial value Read/Write
7 -- 1 --
6 -- 1 --
5 -- 1 --
4 -- 1 --
3 LB3 0 R/W
Large block 3 to 0 0 Not selected 1 Selected
EBR2--Erase block register 2
H'FF83
Flash memory (Flash memory version only)
2 SB2 0 R/W 1 SB1 0 R/W 0 SB0 0 R/W
Bit Initial value Read/Write
7 SB7 0 R/W
6 SB6 0 R/W
5 SB5 0 R/W
4 SB4 0 R/W
3 SB3 0 R/W
Small block 7 to 0 0 Not selected 1 Selected
Rev. 6.00 Sep 12, 2006 page 455 of 526 REJ09B0326-0600
Appendix B Internal I/O Registers
ICRCH--Input capture register CH
Bit Initial value Read/Write 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R
H'F77C
2 0 R 1 0 R
Timer X
0 0 R
ICRCH7 ICRCH6 ICRCH5 ICRCH4 ICRCH3 ICRCH2 ICRCH1 ICRCH0
ICRCL--Input capture register CL
Bit Initial value Read/Write 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R
H'F77D
2 0 R 1 0 R
Timer X
0 0 R
ICRCL7 ICRCL6 ICRCL5 ICRCL4 ICRCL3 ICRCL2 ICRCL1 ICRCL0
ICRDH--Input capture register DH
Bit Initial value Read/Write 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R
H'F77E
2 0 R 1 0 R
Timer X
0 0 R
ICRDH7 ICRDH6 ICRDH5 ICRDH4 ICRDH3 ICRDH2 ICRDH1 ICRDH0
ICRDL--Input capture register DL
Bit Initial value Read/Write 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R
H'F77F
2 0 R 1 0 R
Timer X
0 0 R
ICRDL7 ICRDL6 ICRDL5 ICRDL4 ICRDL3 ICRDL2 ICRDL1 ICRDL0
Rev. 6.00 Sep 12, 2006 page 456 of 526 REJ09B0326-0600
Appendix B Internal I/O Registers
SCR1--Serial control register 1
Bit Initial value Read/Write 7 SNC1 0 R/W 6 SNC0 0 R/W 5 MRKON 0 R/W 4 LTCH 0 R/W 3 CKS3 0 R/W
H'FFA0
2 CKS2 0 R/W 1 CKS1 0 R/W 0
SCI1
CKS0 0 R/W
Clock select (CKS2 to CKS0) Serial Clock Cycle Bit 2 Bit 1 Bit 0 Prescaler Synchronous = 5 MHz = 2.5 MHz CKS2 CKS1 CKS0 Division 0 /1024 0 0 204.8 s 409.6 s 1 /256 51.2 s 102.4 s 1 0 12.8 s 25.6 s /64 6.4 s 12.8 s 1 /32 3.2 s 6.4 s 1 0 0 /16 1.6 s 3.2 s 1 /8 0.8 s 1.6 s 1 0 /4 -- 0.8 s 1 /2 Clock source select (CKS3) 0 Clock source is prescaler S, and pin SCK 1 is output pin 1 Clock source is external clock, and pin SCK 1 is input pin LATCH TAIL select 0 HOLD TAIL is output 1 LATCH TAIL is output TAIL MARK control 0 TAIL MARK is not output (synchronous mode) 1 TAIL MARK is output (SSB mode) Operation mode select 0 0 8-bit synchronous transfer mode 1 16-bit synchronous transfer mode 1 0 Continuous clock output mode 1 Reserved
Rev. 6.00 Sep 12, 2006 page 457 of 526 REJ09B0326-0600
Appendix B Internal I/O Registers
SCSR1--Serial control/status register
H'FFA1
SCI1
Bit Initial value Read/Write
7 -- 1 --
6 SOL 0 R/W
5 ORER 0 R/(W)*
4 -- 1 --
3 -- 1 --
2 -- 1 --
1 MTRF 0 R
0 STF 0 R/W
Start flag 0 Read Write 1 Read Write
Indicates that transfer is stopped Invalid Indicates transfer in progress Starts a transfer operation
TAIL MARK transmit flag 0 Idle state and 8- or -16-bit data transfer in progress 1 TAIL MARK transmission in progress Overrun error flag 0 [Clearing condition] After reading 1, cleared by writing 0 1 [Setting condition] Set if a clock pulse is input after transfer is complete, when an external clock is used Extended data bit 0 Read SO1 pin output level is low Write SO1 pin output level changes to low 1 Read SO1 pin output level is high Write SO1 pin output level changes to high Note: * Only a write of 0 for flag clearing is possible.
Rev. 6.00 Sep 12, 2006 page 458 of 526 REJ09B0326-0600
Appendix B Internal I/O Registers
SDRU--Serial data register U
Bit Initial value Read/Write 7 SDRU7 R/W 6 SDRU6 R/W 5 SDRU5 R/W 4 SDRU4 R/W 3
H'FFA2
2 SDRU2 R/W 1 SDRU1 R/W 0
SCI1
SDRU3 R/W
SDRU0 R/W
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
Stores transmit and receive data 8-bit transfer mode: Not used 16-bit transfer mode: Upper 8 bits of data
SDRL--Serial data register L
Bit Initial value Read/Write 7 SDRL7 R/W 6 SDRL6 R/W 5 SDRL5 R/W 4 SDRL4 R/W 3
H'FFA3
2 SDRL2 R/W 1 SDRL1 R/W 0
SCI1
SDRL3 R/W
SDRL0 R/W
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
Stores transmit and receive data 8-bit transfer mode: 8-bit data 16-bit transfer mode: Lower 8 bits of data
Rev. 6.00 Sep 12, 2006 page 459 of 526 REJ09B0326-0600
Appendix B Internal I/O Registers
SMR--Serial mode register
Bit Initial value Read/Write 7 COM 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 PM 0 R/W 3 STOP 0 R/W
H'FFA8
2 MP 0 R/W 1 CKS1 0 R/W 0
SCI3
CKS0 0 R/W
Clock select 0 0 clock 1 /4 clock 1 0 /16 clock 1 /64 clock Multiprocessor mode 0 Multiprocessor communication function disabled 1 Multiprocessor communication function enabled Stop bit length 0 1 stop bit 1 2 stop bits Parity mode 0 Even parity 1 Odd parity Parity enable 0 Parity bit addition and checking disabled 1 Parity bit addition and checking enabled Character length 0 8-bit data 1 7-bit data Communication mode 0 Asynchronous mode 1 Synchronous mode
Rev. 6.00 Sep 12, 2006 page 460 of 526 REJ09B0326-0600
Appendix B Internal I/O Registers
BRR--Bit rate register
Bit Initial value Read/Write 7 BRR7 1 R/W 6 BRR6 1 R/W 5 BRR5 1 R/W 4 BRR4 1 R/W 3 BRR3 1 R/W
H'FFA9
2 BRR2 1 R/W 1 BRR1 1 R/W 0
SCI3
BRR0 1 R/W
Rev. 6.00 Sep 12, 2006 page 461 of 526 REJ09B0326-0600
Appendix B Internal I/O Registers
SCR3--Serial control register 3
Bit Initial value Read/Write 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W
H'FFAA
2 TEIE 0 R/W 1 CKE1 0 R/W 0
SCI3
CKE0 0 R/W
Clock enable Bit 0 Bit 1 CKE1 CKE0 0 0 1 1 0 1 Communication Mode Asynchronous Synchronous Asynchronous Synchronous Asynchronous Synchronous Asynchronous Synchronous Description Clock Source SCK 3 Pin Function I/O port Internal clock Serial clock output Internal clock Clock output Internal clock Reserved (Do not specify this combination) Clock input External clock Serial clock input External clock Reserved (Do not specify this combination) Reserved (Do not specify this combination)
Transmit end interrupt enable 0 1 Transmit end interrupt request (TEI) disabled Transmit end interrupt request (TEI) enabled
Multiprocessor interrupt enable 0 Multiprocessor interrupt request disabled (normal receive operation) [Clearing condition] When data is received in which the multiprocessor bit is set to 1 Multiprocessor interrupt request enabled The receive interrupt request (RXI), receive error interrupt request (ERI), and setting of the RDRF, FER, and OER flags in the serial status register (SSR), are disabled until data with the multiprocessor bit set to 1 is received.
1
Receive enable 0 1 Receive operation disabled (RXD pin is I/O port) Receive operation enabled (RXD pin is receive data pin)
Transmit enable 0 1 Transmit operation disabled (TXD pin is transmit data pin)*1 Transmit operation enabled (TXD pin is transmit data pin)*1
Note: 1. When bit TXD is set to 1 in PMR7 Receive interrupt enable 0 1 Receive data full interrupt request (RXI) and receive error interrupt request (ERI) disabled Receive data full interrupt request (RXI) and receive error interrupt request (ERI) enabled
Transmit interrupt enable 0 Transmit data empty interrupt request (TXI) disabled 1 Transmit data empty interrupt request (TXI) enabled
Rev. 6.00 Sep 12, 2006 page 462 of 526 REJ09B0326-0600
Appendix B Internal I/O Registers
TDR--Transmit data register
Bit Initial value Read/Write 7 TDR7 1 R/W 6 TDR6 1 R/W 5 TDR5 1 R/W 4 TDR4 1 R/W 3 TDR3 1 R/W
H'FFAB
2 TDR2 1 R/W 1 TDR1 1 R/W 0
SCI3
TDR0 1 R/W
Data for transfer to TSR
Rev. 6.00 Sep 12, 2006 page 463 of 526 REJ09B0326-0600
Appendix B Internal I/O Registers
SSR--Serial status register
Bit Initial value Read/Write 7 TDRE 1 R/(W)* 6 RDRF 0 R/(W)* 5 OER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)*
H'FFAC
2 TEND 1 R 1 MPBR 0 R 0 MPBT 0 R/W
SCI3
Multiprocessor bit transfer 0 1 A 0 multiprocessor bit is transmitted A 1 multiprocessor bit is transmitted
Multiprocessor bit receive 0 1 0 Data in which the multiprocessor bit is 0 has been received Data in which the multiprocessor bit is 1 has been received Transmission in progress [Clearing conditions] * After reading TDRE = 1, cleared by writing 0 to TDRE * When data is written to TDR by an instruction Transmission ended [Setting conditions] * When bit TE in serial control register 3 (SCR3) is cleared to 0 * When bit TDRE is set to 1 when the last bit of a transmit character is sent
Transmit end
1
Parity error 0 1 Reception in progress or completed normally [Clearing condition] After reading PER = 1, cleared by writing 0 to PER A parity error has occurred during reception [Setting condition] When the number of 1 bits in the receive data plus parity bit does not match the parity designated by the parity mode bit (PM) in the serial mode register (SMR) Reception in progress or completed normally [Clearing condition] After reading FER = 1, cleared by writing 0 to FER A framing error has occurred during reception [Setting condition] When the stop bit at the end of the receive data is checked for a value of 1 at completion of reception, and the stop bit is 0 Reception in progress or completed [Clearing condition] After reading OER = 1, cleared by writing 0 to OER An overrun error has occurred during reception [Setting condition] When the next serial reception is completed with RDRF set to 1
Framing error 0 1
Overrun error 0 1
Receive data register full 0 There is no receive data in RDR [Clearing conditions] * After reading RDRF = 1, cleared by writing 0 to RDRF * When RDR data is read by an instruction There is receive data in RDR [Setting condition] When reception ends normally and receive data is transferred from RSR to RDR
1
Transmit data register empty 0 Transmit data written in TDR has not been transferred to TSR [Clearing conditions] * After reading TDRE = 1, cleared by writing 0 to TDRE * When data is written to TDR by an instruction Transmit data has not been written to TDR, or transmit data written in TDR has been transferred to TSR [Setting conditions] * When bit TE in serial control register 3 (SCR3) is cleared to 0 * When data is transferred from TDR to TSR
1
Note: * Only a write of 0 for flag clearing is possible.
Rev. 6.00 Sep 12, 2006 page 464 of 526 REJ09B0326-0600
Appendix B Internal I/O Registers
RDR--Receive data register
Bit Initial value Read/Write 7 RDR7 0 R 6 RDR6 0 R 5 RDR5 0 R 4 RDR4 0 R 3 RDR3 0 R
H'FFAD
2 RDR2 0 R 1 RDR1 0 R 0
SCI3
RDR0 0 R
TMA--Timer mode register A
Bit Initial value Read/Write 7 TMA7 0 R/W 6 TMA6 0 R/W 5 TMA5 0 R/W 4 -- 1 -- 3 TMA3 0 R/W
H'FFB0
2 TMA2 0 R/W 1 TMA1 0 R/W
Timer A
0 TMA0 0 R/W
Clock output select 0 0 0 /32 1 /16 1 0 /8 1 /4 1 0 0 W/32 1 W/16 1 0 W/8 1 W/4
Internal clock select Prescaler and Divider Ratio TMA3 TMA2 TMA1 TMA0 or Overflow Period 0 0 0 0 PSS /8192 1 PSS /4096 PSS /2048 1 0 PSS /512 1 1 0 0 /256 PSS 1 /128 PSS /32 1 0 PSS /8 1 PSS 0 0 0 1s 1 PSW 1 0.5 s PSW 0.25 s 1 0 PSW 0.03125 s 1 PSW 1 0 0 PSW and TCA are reset 1 1 0 1 Function Interval timer
Time base
Rev. 6.00 Sep 12, 2006 page 465 of 526 REJ09B0326-0600
Appendix B Internal I/O Registers
TCA--Timer counter A
Bit Initial value Read/Write 7 TCA7 0 R 6 TCA6 0 R 5 TCA5 0 R 4 TCA4 0 R 3 TCA3 0 R
H'FFB1
2 TCA2 0 R 1 TCA1 0 R
Timer A
0 TCA0 0 R
Count value
TMB1--Timer mode register B1
Bit Initial value Read/Write 7 TMB17 0 R/W 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 --
H'FFB2
2 TMB12 0 R/W 1 TMB11 0 R/W
Timer B1
0 TMB10 0 R/W
Auto-reload function select 0 Interval timer function selected 1 Auto-reload function selected
Clock select 0 0 0 Internal clock: /8192 1 Internal clock: /2048 1 0 Internal clock: /512 1 Internal clock: /256 1 0 0 Internal clock: /64 1 Internal clock: /16 1 0 Internal clock: /4 1 External event (TMIB): Rising or falling edge
Rev. 6.00 Sep 12, 2006 page 466 of 526 REJ09B0326-0600
Appendix B Internal I/O Registers
TCB1--Timer counter B1
Bit Initial value Read/Write 7 TCB17 0 R 6 TCB16 0 R 5 TCB15 0 R 4 TCB14 0 R 3
H'FFB3
2 TCB12 0 R 1 TCB11 0 R
Timer B1
0 TCB10 0 R
TCB13 0 R
Count value
TLB1--Timer load register B1
Bit Initial value Read/Write 7 TLB17 0 W 6 TLB16 0 W 5 TLB15 0 W 4 TLB14 0 W 3 TLB13 0 W
H'FFB3
2 TLB12 0 W 1 TLB11 0 W
Timer B1
0 TLB10 0 W
Reload value
Rev. 6.00 Sep 12, 2006 page 467 of 526 REJ09B0326-0600
Appendix B Internal I/O Registers
TCRV0--Timer control register V0
Bit Initial value Read/Write 7 CMIEB 0 R/W 6 CMIEA 0 R/W 5 OVIE 0 R/W 4 CCLR1 0 R/W 3
H'FFB8
2 CKS2 0 R/W 1 CKS1 0 R/W
Timer V
0 CKS0 0 R/W
CCLR0 0 R/W
Clock select TCRV0 TCRV1 Bit 2 Bit 1 Bit 0 Bit 0 Description CKS2 CKS1 CKS0 ICKS0 -- Clock input disabled 0 0 0 Internal clock: /4, falling edge 0 1 Internal clock: /8, falling edge 1 Internal clock: /16, falling edge 1 0 0 Internal clock: /32, falling edge 1 1 Internal clock: /64, falling edge 0 Internal clock: /128, falling edge 1 0 1 0 -- Clock input disabled 1 -- External clock: rising edge 1 0 -- External clock: falling edge 1 -- External clock: rising and falling edges
Counter clear 1 and 0 0 0 Clearing is disabled 1 Cleared by compare match A 1 0 Cleared by compare match B 1 Cleared by rising edge of external reset input Timer overflow interrupt enable 0 Interrupt request (OVI) from OVF disabled 1 Interrupt request (OVI) from OVF enabled Compare match interrupt enable A 0 Interrupt request (CMIA) from CMFA disabled 1 Interrupt request (CMIA) from CMFA enabled Compare match interrupt enable B 0 Interrupt request (CMIB) from CMFB disabled 1 Interrupt request (CMIB) from CMFB enabled
Rev. 6.00 Sep 12, 2006 page 468 of 526 REJ09B0326-0600
Appendix B Internal I/O Registers
TCSRV--Timer control/status register V
Bit Initial value Read/Write 7 CMFB 0 R/(W)* 6 CMFA 0 R/(W)* 5 OVF 0 R/(W)* 4 -- 1 -- 3 OS3 0 R/W
H'FFB9
2 OS2 0 R/W 1 OS1 0 R/W 0
Timer V
OS0 0 R/W
Output select 0 0 No change at compare match A 1 0 output at compare match A 1 0 1 output at compare match A 1 Output toggles at compare match A Output select 0 0 No change at compare match B 1 0 output at compare match B 1 0 1 output at compare match B 1 Output toggles at compare match B Timer overflow flag 0 [Clearing condition] After reading OVF = 1, cleared by writing 0 to OVF 1 [Setting condition] Set when TCNTV overflows from H'FF to H'00 Compare match flag A 0 [Clearing condition] After reading CMFA = 1, cleared by writing 0 to CMFA 1 [Setting condition] Set when the TCNTV value matches the TCORA value Compare match flag B 0 [Clearing condition] After reading CMFB = 1, cleared by writing 0 to CMFB 1 [Setting condition] Set when the TCNTV value matches the TCORB value
Note: * Only a write of 0 for flag clearing is possible.
Rev. 6.00 Sep 12, 2006 page 469 of 526 REJ09B0326-0600
Appendix B Internal I/O Registers
TCORA--Time constant register A
Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W
H'FFBA
2 1 R/W 1 1 R/W
Timer V
0 1 R/W
TCORA7 TCORA6 TCORA5 TCORA4 TCORA3 TCORA2 TCORA1 TCORA0
TCORB--Time constant register B
Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W
H'FFBB
2 1 R/W 1 1 R/W
Timer V
0 1 R/W
TCORB7 TCORB6 TCORB5 TCORB4 TCORB3 TCORB2 TCORB1 TCORB0
TCNTV--Timer counter V
Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W
H'FFBC
2 0 R/W 1 0 R/W
Timer V
0 0 R/W
TCNTV7 TCNTV6 TCNTV5 TCNTV4 TCNTV3 TCNTV2 TCNTV1 TCNTV0
Rev. 6.00 Sep 12, 2006 page 470 of 526 REJ09B0326-0600
Appendix B Internal I/O Registers
TCRV1--Timer control register V1
Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 TVEG1 0 R/W 3
H'FFBD
2 TRGE 0 R/W 1 -- 1 --
Timer V
0 ICKS0 0 R/W
TVEG0 0 R/W
Internal clock select Selects the TCNTV clock source, with bits CKS2 to CKS0 in TCRV0
TRGV input enable 0 TCNTV counting is not triggered by input at the TRGV pin, and does not stop when TCNTV is cleared by compare match 1 TCNTV counting is triggered by input at the TRGV pin, and stops when TCNTV is cleared by compare match
TRGV input edge select 0 0 TRGV trigger input is disabled 1 Rising edge is selected 1 0 Falling edge is selected 1 Rising and falling edges are both selected
Rev. 6.00 Sep 12, 2006 page 471 of 526 REJ09B0326-0600
Appendix B Internal I/O Registers
TCSRW--Timer control/status register W
Bit Initial value Read/Write 7 B6WI 1 R 6 TCWE 0 R/(W)* 5 B4WI 1 R 4 TCSRWE 0 R/(W)* 3 B2WI 1 R
H'FFBE
2 WDON 0 R/(W) * 1
Watchdog timer
0 WRST 0 R/(W) *
B0WI 1 R
Watchdog timer reset 0 [Clearing conditions] * Reset by RES pin * When TCSRWE = 1, and 0 is written in both B0WI and WRST 1 [Setting condition] When TCW overflows and a reset signal is generated Bit 0 write inhibit 0 Bit 0 is write-enabled 1 Bit 0 is write-protected Watchdog timer on 0 Watchdog timer operation is disabled 1 Watchdog timer operation is enabled Bit 2 write inhibit 0 Bit 2 is write-enabled 1 Bit 2 is write-protected Timer control/status register W write enable 0 Data cannot be written to TCSRW bits 2 and 0 1 Data can be written to TCSRW bits 2 and 0 Bit 4 write inhibit 0 Bit 4 is write-enabled 1 Bit 4 is write-protected Timer counter W write enable 0 Data cannot be written to TCW 1 Data can be written to TCW Bit 6 write inhibit 0 Bit 6 is write-enabled 1 Bit 6 is write-protected Note: * Write is permitted only under certain conditions.
Rev. 6.00 Sep 12, 2006 page 472 of 526 REJ09B0326-0600
Appendix B Internal I/O Registers
TCW--Timer counter W
Bit Initial value Read/Write 7 TCW7 0 R/W 6 TCW6 0 R/W 5 TCW5 0 R/W 4 TCW4 0 R/W 3 TCW3 0 R/W
H'FFBF
2 TCW2 0 R/W
Watchdog timer
1 TCW1 0 R/W 0 TCW0 0 R/W
Count value
Rev. 6.00 Sep 12, 2006 page 473 of 526 REJ09B0326-0600
Appendix B Internal I/O Registers
AMR--A/D mode register
Bit Initial value Read/Write 7 CKS 0 R/W 6 TRGE 0 R/W 5 -- 1 -- 4 -- 1 -- 3 CH3 0 R/W
H'FFC4
2 CH2 0 R/W 1
A/D converter
0 CH0 0 R/W
CH1 0 R/W
Channel select Bit 3 Bit 2 Bit 1 CH3 CH2 CH1 0 0 * 1 0 1 1 0 0 1 1 0 0 1 1 External trigger select
Bit 0 CH0 * 0 1 0 1 0 1 0 1 0 1 0 1
Analog Input Channel No channel selected AN 0 AN 1 AN 2 AN 3 AN 4 AN 5 AN 6 AN 7 Reserved Reserved Reserved Reserved * Don't care
0 Disables start of A/D conversion by exter al trigger 1 Enables start of A/D conversion by rising or falling edge of external trigger at pin ADTRG Clock select Bit 7 CKS Conversion Period 0 62/ 1 31/ Note: *
Conversion Time = 2 MHz = 5 MHz 31 s 15.5 s 12.4 s --*
Operation is not guaranteed if the conversion time is less than 12.4 s. Set bit 7 for a value of at least 12.4 s.
Rev. 6.00 Sep 12, 2006 page 474 of 526 REJ09B0326-0600
Appendix B Internal I/O Registers
ADRR--A/D result register
Bit Initial value Read/Write 7 ADR7 R 6 ADR6 R 5 ADR5 R 4 ADR4 R 3 ADR3 R
H'FFC5
2 ADR2 R 1
A/D converter
0 ADR0 R
ADR1 R
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
A/D conversion result
ADSR--A/D start register
Bit Initial value Read/Write 7 ADSF 0 R/W 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 --
H'FFC6
2 -- 1 -- 1 -- 1 --
A/D converter
0 -- 1 --
A/D status flag 0 Read Indicates completion of A/D conversion Write Stops A/D conversion 1 Read Indicates A/D conversion in progress Write Starts A/D conversion
Rev. 6.00 Sep 12, 2006 page 475 of 526 REJ09B0326-0600
Appendix B Internal I/O Registers
PWCR--PWM control register
Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 --
H'FFD0
2 -- 1 -- 1 -- 1 --
14-bit PWM
0 PWCR0 0 W
Clock select 0 The input clock is /2 (t * = 2/). The conversion period is 16,384/, with a minimum modulation width of 1/. 1 The input clock is /4 (t * = 4/). The conversion period is 32,768/, with a minimum modulation width of 2/.
Note: * t: Period of PWM input clock
PWDRU--PWM data register U
Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 0 W 4 0 W 3 0 W
H'FFD1
2 0 W 1 0 W
14-bit PWM
0 0 W
PWDRU5 PWDRU4PWDRU3 PWDRU2 PWDRU1 PWDRU0
Upper 6 bits of data for generating PWM waveform
PWDRL--PWM data register L
Bit Initial value Read/Write 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W
H'FFD2
2 0 W 1 0 W
14-bit PWM
0 0 W
PWDRL7 PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0
Lower 8 bits of data for generating PWM waveform
Rev. 6.00 Sep 12, 2006 page 476 of 526 REJ09B0326-0600
Appendix B Internal I/O Registers
PDR1--Port data register 1
Bit Initial value Read/Write 7 P17 0 R/W 6 P16 0 R/W 5 P15 0 R/W 4 P14 0 R/W 3 -- 0 --
H'FFD4
2 -- 0 -- 1 -- 0 --
I/O ports
0 P10 0 R/W
PDR2--Port data register 2
Bit Initial value Read/Write 7 -- 0 -- 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- 3 -- 0 --
H'FFD5
2 P22 0 R/W 1 P21 0 R/W
I/O ports
0 P20 0 R/W
PDR3--Port data register 3
Bit Initial value Read/Write 7 -- 0 -- 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- 3 -- 0 --
H'FFD6
2 P32 0 R/W 1 P31 0 R/W
I/O ports
0 P30 0 R/W
PDR5--Port data register 5
Bit Initial value Read/Write 7 P5 7 0 R/W 6 P56 0 R/W 5 P55 0 R/W 4 P54 0 R/W 3 P53 0 R/W
H'FFD8
2 P52 0 R/W 1 P51 0 R/W
I/O ports
0 P50 0 R/W
PDR6--Port data register 6
Bit Initial value Read/Write 7 P6 7 0 R/W 6 P66 0 R/W 5 P65 0 R/W 4 P64 0 R/W 3 P63 0 R/W
H'FFD9
2 P62 0 R/W 1 P61 0 R/W
I/O ports
0 P60 0 R/W
Rev. 6.00 Sep 12, 2006 page 477 of 526 REJ09B0326-0600
Appendix B Internal I/O Registers
PDR7--Port data register 7
Bit Initial value Read/Write 7 P7 7 0 R/W 6 P76 0 R/W 5 P75 0 R/W 4 P74 0 R/W 3 P73 0 R/W
H'FFDA
2 -- 0 -- 1 -- 0 --
I/O ports
0 -- 0 --
PDR8--Port data register 8
Bit Initial value Read/Write 7 P8 7 0 R/W 6 P86 0 R/W 5 P85 0 R/W 4 P84 0 R/W 3 P83 0 R/W
H'FFDB
2 P82 0 R/W 1 P81 0 R/W
I/O ports
0 P80 0 R/W
PDR9--Port data register 9
Bit Initial value Read/Write 7 -- 0 -- 6 -- 0 -- 5 -- 0 -- 4 P94 0 R/W 3 P93 0 R/W
H'FFDC
2 P92 0 R/W 1 P91 0 R/W
I/O ports
0 P90 0 R/W
PDRB--Port data register B
Bit 7 PB 7 Read/Write R 6 PB 6 R 5 PB 5 R 4 PB 4 R 3 PB 3 R
H'FFDD
2 PB 2 R 1 PB 1 R
I/O ports
0 PB 0 R
Rev. 6.00 Sep 12, 2006 page 478 of 526 REJ09B0326-0600
Appendix B Internal I/O Registers
PCR1--Port control register 1
Bit Initial value Read/Write 7 PCR17 0 W 6 PCR16 0 W 5 PCR15 0 W 4 PCR14 0 W 3 -- 0 --
H'FFE4
2 -- 0 -- 1 -- 0 --
I/O ports
0 PCR10 0 W
Port 1 input/output select 0 Input pin 1 Output pin
PCR2--Port control register 2
Bit Initial value Read/Write 7 -- 0 -- 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- 3 -- 0 --
H'FFE5
2 PCR22 0 W 1 PCR21 0 W
I/O ports
0 PCR20 0 W
Port 2 input/output select 0 Input pin 1 Output pin
PCR3--Port control register 3
Bit Initial value Read/Write 7 -- 0 -- 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- 3 -- 0 --
H'FFE6
2 PCR32 0 W 1 PCR31 0 W
I/O ports
0 PCR30 0 W
Port 3 input/output select 0 Input pin 1 Output pin
Rev. 6.00 Sep 12, 2006 page 479 of 526 REJ09B0326-0600
Appendix B Internal I/O Registers
PCR5--Port control register 5
Bit Initial value Read/Write 7 PCR57 0 W 6 PCR56 0 W 5 PCR55 0 W 4 PCR54 0 W 3 PCR53 0 W
H'FFE8
2 PCR52 0 W 1 PCR51 0 W
I/O ports
0 PCR50 0 W
Port 5 input/output select 0 Input pin 1 Output pin
PCR6--Port control register 6
Bit Initial value Read/Write 7 PCR6 7 0 W 6 PCR6 6 0 W 5 PCR6 5 0 W 4 PCR6 4 0 W 3
H'FFE9
2 PCR6 2 0 W 1 PCR6 1 0 W
I/O ports
0 PCR6 0 0 W
PCR6 3 0 W
Port 6 input/output select 0 Input pin 1 Output pin
PCR7--Port control register 7
Bit Initial value Read/Write 7 PCR77 0 W 6 PCR76 0 W 5 PCR75 0 W 4 PCR74 0 W 3 PCR73 0 W
H'FFEA
2 -- 0 -- 1 -- 0 --
I/O ports
0 -- 0 --
Port 7 input/output select 0 Input pin 1 Output pin
Rev. 6.00 Sep 12, 2006 page 480 of 526 REJ09B0326-0600
Appendix B Internal I/O Registers
PCR8--Port control register 8
Bit Initial value Read/Write 7 PCR87 0 W 6 PCR86 0 W 5 PCR85 0 W 4 PCR84 0 W 3 PCR83 0 W
H'FFEB
2 PCR82 0 W 1 PCR81 0 W
I/O ports
0 PCR80 0 W
Port 8 input/output select 0 Input pin 1 Output pin
PCR9--Port control register 9
Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 0 -- 4 PCR9 4 0 W 3 0 W
H'FFEC
2 0 W 1 PCR91 0 W
I/O ports
0 PCR90 0 W
PCR9 3 PCR92
Port 9 input/output select 0 Input pin 1 Output pin
PUCR1--Port pull-up control register 1
Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 -- 0 --
H'FFED
2 -- 0 -- 1 -- 0 --
I/O ports
0 PUCR10 0 R/W
PUCR17 PUCR16 PUCR15 PUCR14
PUCR3--Port pull-up control register 3
H'FFEE
I/O ports
Bit Initial value Read/Write
7 -- 0 --
6 -- 0 --
5 -- 0 --
4 -- 0 --
3 -- 0 --
2 0 R/W
1 0 R/W
0 0 R/W
PUCR32 PUCR31 PUCR30
Rev. 6.00 Sep 12, 2006 page 481 of 526 REJ09B0326-0600
Appendix B Internal I/O Registers
PUCR5--Port pull-up control register 5
Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W
H'FFEF
2 0 R/W 1 0 R/W
I/O ports
0 0 R/W
PUCR5 7 PUCR56 PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50
SYSCR1--System control register 1
Bit Initial value Read/Write 7 SSBY 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 LSON 0 R/W
H'FFF0
2 -- 1 -- 1
System control
0 MA0 1 R/W
MA1 1 R/W
Active (medium-speed) mode clock select 0 0 osc /16 1 osc /32 1 0 osc /64 1 osc/128 Low speed on flag 0 The CPU operates on the system clock () 1 The CPU operates on the subclock ( SUB) Standby timer select 2 to 0 0 0 0 Wait time = 8,192 states 1 Wait time = 16,384 states 1 0 Wait time = 32,768 states 1 Wait time = 65,536 states 1 * * Wait time = 131,072 states Software standby * Don't care
0 * When a SLEEP instruction is executed in active mode, a transition is made to sleep mode * When a SLEEP instruction is executed in subactive mode, a transition is made to subsleep mode 1 * When a SLEEP instruction is executed in active mode, a transition is made to standby mode or watch mode * When a SLEEP instruction is executed in subactive mode, a transition is made to watch mode
Rev. 6.00 Sep 12, 2006 page 482 of 526 REJ09B0326-0600
Appendix B Internal I/O Registers
SYSCR2--System control register 2
H'FFF1
System control
Bit Initial value Read/Write
7 -- 1 --
6 -- 1 --
5 -- 1 --
4 NESEL 0 R/W
3 DTON 0 R/W
2 MSON 0 R/W
1 SA1 0 R/W
0 SA0 0 R/W
Subactive mode clock select 0 0 W/8 1 W/4 1 * W/2 Medium speed on flag * Don't care 0 * Operates in active (high-speed) mode after exit from standby, watch, or sleep mode * Operates in sleep (high-speed) mode if a SLEEP instruction is executed in active mode 1 * Operates in active (medium-speed) mode after exit from standby, watch, or sleep mode * Operates in sleep (medium-speed) mode if a SLEEP instruction is executed in active mode Direct transfer on flag 0 * When a SLEEP instruction is executed in active mode, a transition is made to standby mode, watch mode, or sleep mode * When a SLEEP instruction is executed in subactive mode, a transition is made to watch mode or subsleep mode 1 * When a SLEEP instruction is executed in active (high-speed) mode, a direct transition is made to active (medium-speed) mode if SSBY = 0, MSON = 1, and LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1 * When a SLEEP instruction is executed in active (medium-speed) mode, a direct transition is made to active (high-speed) mode if SSBY = 0, MSON = 0, and LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1 * When a SLEEP instruction is executed in subactive mode, a direct transition is made to active (high-speed) mode if SSBY = 1, TMA3 = 1, LSON = 0, and MSON = 0, or to active (medium-speed) mode if SSBY = 1, TMA3 = 1, LSON = 0, and MSON = 1 Noise elimination sampling frequency select 0 Sampling rate is OSC/16 1 Sampling rate is OSC/4
Rev. 6.00 Sep 12, 2006 page 483 of 526 REJ09B0326-0600
Appendix B Internal I/O Registers
IEGR1--Interrupt edge select register 1
Bit Initial value Read/Write 7 -- 0 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 IEG3 0 R/W
H'FFF2
2 IEG2 0 R/W 1
System control
0 IEG0 0 R/W
IEG1 0 R/W
IRQ0 edge select 0 Falling edge of IRQ0 pin input is detected 1 Rising edge of IRQ0 pin input is detected IRQ1 edge select 0 Falling edge of IRQ1 pin input is detected 1 Rising edge of IRQ1 pin input is detected IRQ2 edge select 0 Falling edge of IRQ2 pin input is detected 1 Rising edge of IRQ2 pin input is detected IRQ3 edge select 0 Falling edge of IRQ3 pin input is detected 1 Rising edge of IRQ3 pin input is detected
Rev. 6.00 Sep 12, 2006 page 484 of 526 REJ09B0326-0600
Appendix B Internal I/O Registers
IEGR2--Interrupt edge select register 2
Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W
H'FFF3
2 0 R/W 1 0
System control
0 0 R/W
INTEG7 INTEG6 INTEG5 INTEG4 INTEG3 INTEG2 INTEG1 INTEG0 R/W
INT4 to INT0 edge select 0 Falling edge of INTn pin input is detected 1 Rising edge of INTn pin input is detected (n = 4 to 0) INT5 edge select 0 Falling edge of INT5 and ADTRG pin input is detected 1 Rising edge of INT5 and ADTRG pin input is detected INT6 edge select 0 Falling edge of INT6 and TMIB pin input is detected 1 Rising edge of INT6 and TMIB pin input is detected INT7 edge select 0 Falling edge of INT7 pin input is detected 1 Rising edge of INT7 pin input is detected
Rev. 6.00 Sep 12, 2006 page 485 of 526 REJ09B0326-0600
Appendix B Internal I/O Registers
IENR1--Interrupt enable register 1
Bit Initial value Read/Write 7 IENTB1 0 R/W 6 IENTA 0 R/W 5 -- 0 -- 4 -- 1 -- 3 IEN3 0 R/W
H'FFF4
2 IEN2 0 R/W 1
System control
0 IEN0 0 R/W
IEN1 0 R/W
IRQ3 to IRQ0 interrupt enable 0 Disables IRQ3 to IRQ0 interrupt requests 1 Enables IRQ3 to IRQ0 interrupt requests Timer A interrupt enable 0 Disables timer A interrupt requests 1 Enables timer A interrupt requests Timer B1 interrupt enable 0 Disables timer B1 interrupt requests 1 Enables timer B1 interrupt requests
Rev. 6.00 Sep 12, 2006 page 486 of 526 REJ09B0326-0600
Appendix B Internal I/O Registers
IENR2--Interrupt enable register 2
Bit Initial value Read/Write 7 IENDT 0 R/W 6 IENAD 0 R/W 5 -- 0 -- 4 IENS1 0 R/W 3 -- 0 --
H'FFF5
2 -- 0 -- 1 -- 0 --
System control
0 -- 0 --
SCI1 interrupt enable 0 Disables SCI1 interrupt requests 1 Enables SCI1 interrupt requests A/D converter interrupt enable 0 Disables A/D converter interrupt requests 1 Enables A/D converter interrupt requests Direct transfer interrupt enable 0 Disables direct transfer interrupt requests 1 Enables direct transfer interrupt requests
IENR3--Interrupt enable register 3
H'FFF6
System control
Bit Initial value Read/Write
7 0 R/W
6 0 R/W
5 0 R/W
4 0 R/W
3 0 R/W
2 0 R/W
1 0 R/W
0 0 R/W
INTEN7 INTEN6 INTEN5 INTEN4 INTEN3 INTEN2 INTEN1 INTEN0
INT7 to INT0 interrupt enable 0 Disables INT7 to INT0 interrupt requests 1 Enables INT7 to INT0 interrupt requests
Rev. 6.00 Sep 12, 2006 page 487 of 526 REJ09B0326-0600
Appendix B Internal I/O Registers
IRR1--Interrupt request register 1
Bit Initial value Read/Write 7 IRRTB1 0 R/W * 6 IRRTA 0 R/W * 5 -- 0 -- 4 -- 1 -- 3 IRRI3 0
H'FFF7
2 IRRI2 0 R/W * 1
System control
0 IRRI0 0 R/W *
IRRI1 0 R/W *
R/W *
IRQ3 to IRQ0 interrupt request flag 0 [Clearing condition] When IRRIn = 1, it is cleared by writing 0 1 [Setting condition] When pin IRQn is set for interrupt input and the designated signal edge is input (n = 3 to 0) Timer A interrupt request flag 0 [Clearing condition] When IRRTA = 1, it is cleared by writing 0 1 [Setting condition] When timer counter A overflows from H'FF to H'00 Timer B1 interrupt request flag 0 [Clearing condition] When IRRTB1 = 1, it is cleared by writing 0 1 [Setting condition] When timer counter B1 overflows from H'FF to H'00
Note: * Only a write of 0 for flag clearing is possible.
Rev. 6.00 Sep 12, 2006 page 488 of 526 REJ09B0326-0600
Appendix B Internal I/O Registers
IRR2--Interrupt request register 2
Bit Initial value Read/Write 7 IRRDT 0 R/W * 6 IRRAD 0 R/W * 5 -- 0 -- 4 IRRS1 0 R/W * 3 -- 0 --
H'FFF8
2 -- 0 -- 1
System control
0 -- 0 --
-- 0 --
SCI1 interrupt request flag 0 [Clearing condition] When IRRS1 = 1, it is cleared by writing 0 1 [Setting condition] When an SCI1 transfer is completed
A/D converter interrupt request flag 0 [Clearing condition] When IRRAD = 1, it is cleared by writing 0 1 [Setting condition] When A/D conversion is completed and ADSF is cleared to 0 in ADSR
Direct transfer interrupt request flag 0 [Clearing condition] When IRRDT = 1, it is cleared by writing 0 1 [Setting condition] A SLEEP instruction is executed when DTON = 1 and a direct transfer is made Note: * Only a write of 0 for flag clearing is possible.
Rev. 6.00 Sep 12, 2006 page 489 of 526 REJ09B0326-0600
Appendix B Internal I/O Registers
IRR3--Interrupt request register 3
Bit Initial value Read/Write 7 INTF7 0 R/W * 6 INTF6 0 R/W * 5 INTF5 0 R/W * 4 INTF4 0 R/W 3 INTF3 0
H'FFF9
2 INTF2 0 R/W * 1
System control
0 INTF0 0 R/W *
INTF1 0 R/W *
R/W *
INT7 to INT0 interrupt request flag 0 [Clearing condition] When INTFn = 1, it is cleared by writing 0 1 [Setting condition] When the designated signal edge is input at pin INTn (n = 7 to 0) Note: * Only a write of 0 for flag clearing is possible.
Rev. 6.00 Sep 12, 2006 page 490 of 526 REJ09B0326-0600
Appendix B Internal I/O Registers
PMR1--Port mode register 1
Bit Initial value Read/Write 7 IRQ3 0 R/W 6 IRQ2 0 R/W 5 IRQ1 0 R/W 4 PWM 0 R/W 3 -- 0 --
H'FFFC
2 -- 1 -- 1 -- 0 --
I/O ports
0 TMOW 0 R/W
P10/TMOW pin function switch 0 Functions as P10 I/O pin 1 Functions as TMOW output pin P14/PWM pin function switch 0 Functions as P14 I/O pin 1 Functions as PWM output pin P15/IRQ1 pin function switch 0 Functions as P15 I/O pin 1 Functions as IRQ1 input pin P16/IRQ2 pin function switch 0 Functions as P16 I/O pin 1 Functions as IRQ2 input pin P17/IRQ3 pin function switch 0 Functions as P17 I/O pin 1 Functions as IRQ3/TRGV input pin
Rev. 6.00 Sep 12, 2006 page 491 of 526 REJ09B0326-0600
Appendix B Internal I/O Registers
PMR3--Port mode register 3
Bit Initial value Read/Write 7 -- 0 -- 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- 3 -- 0 --
H'FFFD
2 SO1 0 R/W 1 SI1 0 R/W
I/O ports
0 SCK1 0 R/W
P30/SCK1 pin function switch 0 Functions as P30 I/O pin 1 Functions as SCK1 I/O pin P31/SI1 pin function switch 0 Functions as P31 I/O pin 1 Functions as SI1 input pin P32/SO1 pin function switch 0 Functions as P32 I/O pin 1 Functions as SO1 output pin
PMR7--Port mode register 7
Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 --
H'FFFF
2 TXD 0 R/W 1 -- 0 --
I/O ports
0 POF1 0 R/W
P32/SO1 pin PMOS control 0 CMOS output 1 NMOS open-drain output P22/TXD pin function switch (TXD) 0 Functions as P22 I/O pin 1 Functions as TXD output pin
Rev. 6.00 Sep 12, 2006 page 492 of 526 REJ09B0326-0600
Appendix C I/O Port Block Diagrams
Appendix C I/O Port Block Diagrams
C.1 Block Diagrams of Port 1
SBY RES (low level during reset and in standby mode) VCC VCC PMR1n
PUCR1n
P1n
PDR1n
Internal data bus
VSS
PCR1n
IRQn-4
Legend: PDR1: Port data register 1 PCR1: Port control register 1 PMR1: Port mode register 1 PUCR1: Port pull-up control register 1 Note: n = 7 or 6
Figure C.1 (a) Port 1 Block Diagram (Pins P17 and P16)
Rev. 6.00 Sep 12, 2006 page 493 of 526 REJ09B0326-0600
Appendix C I/O Port Block Diagrams
SBY (low level during reset and in standby mode) VCC VCC
RES
PUCR15
PMR15
P15
PDR15
Internal data bus
VSS
PCR15
IRQ1
Legend: PDR1: PCR1: PMR1: PUCR1:
Port data register 1 Port control register 1 Port mode register 1 Port pull-up control register 1
Figure C.1 (b) Port 1 Block Diagram (Pin P15)
Rev. 6.00 Sep 12, 2006 page 494 of 526 REJ09B0326-0600
Appendix C I/O Port Block Diagrams
PWM module PWM
RES SBY (low level during reset and in standby mode) PUCR14 VCC VCC PMR14
P14
PDR14
Internal data bus
VSS
PCR14
Legend: PDR1: PCR1: PMR1: PUCR1:
Port data register 1 Port control register 1 Port mode register 1 Port pull-up control register 1
Figure C.1 (c) Port 1 Block Diagram (Pin P14)
Rev. 6.00 Sep 12, 2006 page 495 of 526 REJ09B0326-0600
Appendix C I/O Port Block Diagrams
Timer A module TMOW
RES SBY (low level during reset and in standby mode) PUCR10 VCC VCC PMR10
P10
PDR10
Internal data bus
VSS
PCR10
Legend: PDR1: PCR1: PMR1: PUCR1:
Port data register 1 Port control register 1 Port mode register 1 Port pull-up control register 1
Figure C.1 (d) Port 1 Block Diagram (Pin P10)
Rev. 6.00 Sep 12, 2006 page 496 of 526 REJ09B0326-0600
Appendix C I/O Port Block Diagrams
C.2
Block Diagrams of Port 2
SBY
PMR72 VCC SCI3 module TXD Internal data bus
P22
PDR22
VSS
PCR22
Legend: PDR2: Port data register 2 PCR2: Port control register 2 PMR7: Port mode register 7
Figure C.2 (a) Port 2 Block Diagram (Pin P22)
Rev. 6.00 Sep 12, 2006 page 497 of 526 REJ09B0326-0600
Appendix C I/O Port Block Diagrams
SBY
VCC
SCI3 module RE RXD
P21
PDR21 Internal data bus
VSS
PCR21
Legend: PDR2: Port data register 2 PCR2: Port control register 2
Figure C.2 (b) Port 2 Block Diagram (Pin P21)
Rev. 6.00 Sep 12, 2006 page 498 of 526 REJ09B0326-0600
Appendix C I/O Port Block Diagrams
SBY SCI3 module VCC SCKIE SCKOE SCKO SCKI P20 PDR20 Internal data bus
VSS
PCR20
Legend: PDR2: Port data register 2 PCR2: Port control register 2
Figure C.2 (c) Port 2 Block Diagram (Pin P20)
Rev. 6.00 Sep 12, 2006 page 499 of 526 REJ09B0326-0600
Appendix C I/O Port Block Diagrams
C.3
Block Diagrams of Port 3
SCI1 module SO1 PMR70
RES SBY (low level during reset and in standby mode)
PUCR32 VCC VCC PMR32
P32
PDR32
Internal data bus
VSS
PCR32
Legend: PDR3: PCR3: PMR3: PMR7: PUCR3:
Port data register 3 Port control register 3 Port mode register 3 Port mode register 7 Port pull-up control register 3
Figure C.3 (a) Port 3 Block Diagram (Pin P32)
Rev. 6.00 Sep 12, 2006 page 500 of 526 REJ09B0326-0600
Appendix C I/O Port Block Diagrams
SBY (low level during reset and in standby mode) VCC VCC
RES
PUCR31
PMR31
P31
PDR31
Internal data bus
VSS
PCR31
SCI1 module SI1
Legend: PDR3: PCR3: PMR3: PUCR3:
Port data register 3 Port control register 3 Port mode register 3 Port pull-up control register 3
Figure C.3 (b) Port 3 Block Diagram (Pin P31)
Rev. 6.00 Sep 12, 2006 page 501 of 526 REJ09B0326-0600
Appendix C I/O Port Block Diagrams
RES SBY (low level during reset and in standby mode) SCI1 module CKS3 SCK0 SCK1 PUCR30 VCC VCC PMR30
P30
PDR30
VSS
PCR30
Legend: PDR3: PCR3: PMR3: PUCR3:
Port data register 3 Port control register 3 Port mode register 3 Port pull-up control register 3
Figure C.3 (c) Port 3 Block Diagram (Pin P30)
Rev. 6.00 Sep 12, 2006 page 502 of 526 REJ09B0326-0600
Internal data bus
Appendix C I/O Port Block Diagrams
C.4
Block Diagrams of Port 5
SBY (low level during reset and in standby mode) VCC VCC
Internal data bus
RES
PUCR5n
P5n
PDR5n
VSS
PCR5n
INT module INTn
Legend: PDR5: Port data register 5 PCR5: Port control register 5 PUCR5: Port pull-up control register 5 Note: n = 7, 4 to 0
Figure C.4 (a) Port 5 Block Diagram (Pins P57 and P54 to P50)
Rev. 6.00 Sep 12, 2006 page 503 of 526 REJ09B0326-0600
Appendix C I/O Port Block Diagrams
SBY (low level during reset and in standby mode) VCC VCC
PUCR56
Timer B1 module TMIB
P56
PDR56
VSS
PCR56
Internal data bus
INT module INT6 Legend: PDR5: Port data register 5 PCR5: Port control register 5 PUCR5: Port pull-up control register 5
Figure C.4 (b) Port 5 Block Diagram (Pin P56)
Rev. 6.00 Sep 12, 2006 page 504 of 526 REJ09B0326-0600
Appendix C I/O Port Block Diagrams
SBY (low level during reset and in standby mode) VCC VCC
Internal data bus
RES A/D module ADTRG
PUCR55
P55
PDR55
VSS
PCR55
INT module INT5 Legend: PDR5: Port data register 5 PCR5: Port control register 5 PUCR5: Port pull-up control register 5
Figure C.4 (c) Port 5 Block Diagram (Pin P55)
Rev. 6.00 Sep 12, 2006 page 505 of 526 REJ09B0326-0600
Appendix C I/O Port Block Diagrams
C.5
Block Diagram of Port 6
SBY (low level during reset and in standby mode)
VCC
P6n
PDR6n Internal data bus
VSS
PCR6n
Legend: PDR6: Port data register 6 PCR6: Port control register 6 Note: n = 7 to 0
Figure C.5 Port 6 Block Diagram (Pins P67 to P60)
Rev. 6.00 Sep 12, 2006 page 506 of 526 REJ09B0326-0600
Appendix C I/O Port Block Diagrams
C.6
Block Diagrams of Port 7
SBY (low level during reset and in standby mode)
VCC
P7n
PDR7n
Internal data bus
VSS
PCR7n
Legend: PDR7: Port data register 7 PCR7: Port control register 7 Note: n = 7 or 3
Figure C.6 (a) Port 7 Block Diagram (Pins P77 and P73)
Rev. 6.00 Sep 12, 2006 page 507 of 526 REJ09B0326-0600
Appendix C I/O Port Block Diagrams
SBY (low level during reset and in standby mode) Timer V module VCC TMOV PDR76 0S3 to 0S0
P76
VSS
PCR76
Internal data bus
Legend: PDR7: Port data register 7 PCR7: Port control register 7
Figure C.6 (b) Port 7 Block Diagram (Pin P76)
Rev. 6.00 Sep 12, 2006 page 508 of 526 REJ09B0326-0600
Appendix C I/O Port Block Diagrams
SBY (low level during reset and in standby mode)
VCC
P75
PDR75
Internal data bus
VSS
PCR75
Timer V module TMCIV
Legend: PDR7: Port data register 7 PCR7: Port control register 7
Figure C.6 (c) Port 7 Block Diagram (Pin P75)
Rev. 6.00 Sep 12, 2006 page 509 of 526 REJ09B0326-0600
Appendix C I/O Port Block Diagrams
SBY (low level during reset and in standby mode)
VCC
P74
PDR74
Internal data bus
VSS
PCR74
Timer V module TMRIV
Legend: PDR7: Port data register 7 PCR7: Port control register 7
Figure C.6 (d) Port 7 Block Diagram (Pin P74)
Rev. 6.00 Sep 12, 2006 page 510 of 526 REJ09B0326-0600
Appendix C I/O Port Block Diagrams
C.7
Block Diagrams of Port 8
SBY (low level during reset and in standby mode)
VCC
P87
PDR87
Internal data bus
VSS
PCR87
Legend: PDR8: Port data register 8 PCR8: Port control register 8
Figure C.7 (a) Port 8 Block Diagram (Pin P87)
Rev. 6.00 Sep 12, 2006 page 511 of 526 REJ09B0326-0600
Appendix C I/O Port Block Diagrams
SBY (low level during reset and in standby mode)
VCC
P86
PDR86
Internal data bus
VSS
PCR86
Timer X module FTID
Legend: PDR8: Port data register 8 PCR8: Port control register 8
Figure C.7 (b) Port 8 Block Diagram (Pin P86)
Rev. 6.00 Sep 12, 2006 page 512 of 526 REJ09B0326-0600
Appendix C I/O Port Block Diagrams
SBY (low level during reset and in standby mode)
VCC
P85
PDR85
Internal data bus
VSS
PCR85
Timer X module FTIC
Legend: PDR8: Port data register 8 PCR8: Port control register 8
Figure C.7 (c) Port 8 Block Diagram (Pin P85)
Rev. 6.00 Sep 12, 2006 page 513 of 526 REJ09B0326-0600
Appendix C I/O Port Block Diagrams
SBY (low level during reset and in standby mode)
VCC
P84
PDR84
Internal data bus
VSS
PCR84
Timer X module FTIB
Legend: PDR8: Port data register 8 PCR8: Port control register 8
Figure C.7 (d) Port 8 Block Diagram (Pin P84)
Rev. 6.00 Sep 12, 2006 page 514 of 526 REJ09B0326-0600
Appendix C I/O Port Block Diagrams
SBY (low level during reset and in standby mode)
VCC
P83
PDR83
Internal data bus
VSS
PCR83
Timer X module FTIA
Legend: PDR8: Port data register 8 PCR8: Port control register 8
Figure C.7 (e) Port 8 Block Diagram (Pin P83)
Rev. 6.00 Sep 12, 2006 page 515 of 526 REJ09B0326-0600
Appendix C I/O Port Block Diagrams
SBY (low level during reset and in standby mode)
VCC
Timer X module OEB FTOB
P82
PDR82
VSS
PCR82
Internal data bus
Legend: PDR8: Port data register 8 PCR8: Port control register 8
Figure C.7 (f) Port 8 Block Diagram (Pin P82)
Rev. 6.00 Sep 12, 2006 page 516 of 526 REJ09B0326-0600
Appendix C I/O Port Block Diagrams
SBY (low level during reset and in standby mode)
VCC
Timer X module OEA FTOA
P81
PDR81
VSS
PCR81
Internal data bus
Legend: PDR8: Port data register 8 PCR8: Port control register 8
Figure C.7 (g) Port 8 Block Diagram (Pin P81)
Rev. 6.00 Sep 12, 2006 page 517 of 526 REJ09B0326-0600
Appendix C I/O Port Block Diagrams
SBY (low level during reset and in standby mode)
VCC
P80
PDR80
Internal data bus
VSS
PCR80
Timer X module FTCI
Legend: PDR8: Port data register 8 PCR8: Port control register 8
Figure C.7 (h) Port 8 Block Diagram (Pin P80)
Rev. 6.00 Sep 12, 2006 page 518 of 526 REJ09B0326-0600
Appendix C I/O Port Block Diagrams
C.8
Block Diagram of Port 9
SBY (low level during reset and in standby mode)
VCC
P9n
PDR9n
Internal data bus
VSS
PCR9n
Legend: PDR9: Port data register 9 PCR9: Port control register 9 Note: n = 4 to 0
Figure C.8 Port 9 Block Diagram (Pins P94 to P90)
Rev. 6.00 Sep 12, 2006 page 519 of 526 REJ09B0326-0600
Appendix C I/O Port Block Diagrams
C.9
Block Diagram of Port B
Internal data bus
PBn
A/D module DEC AMR3 to AMR0
VIN
Note:
n = 7 to 0
Figure C.9 Port B Block Diagram (Pins PB7 to PB0)
Rev. 6.00 Sep 12, 2006 page 520 of 526 REJ09B0326-0600
Appendix D Port States in the Different Processing States
Appendix D Port States in the Different Processing States
Table D.1
Port
Port States Overview
Reset Sleep Subsleep Standby Retained Retained Retained Retained Retained Retained Retained Retained Watch Subactive Active Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions
Retained P17 to P14, High P10 impedance P22 to P20 P32 to P30 P57 to P50 P67 to P60 P77 to P73 P87 to P80 P94 to P90 High Retained impedance High Retained impedance High Retained impedance High Retained impedance High Retained impedance High Retained impedance High Retained impedance
Retained High impedance* High Retained impedance Retained High impedance* Retained High impedance* High Retained impedance High Retained impedance High Retained impedance High Retained impedance
PB7 to PB0 High High High High High High High impedance impedance impedance impedance impedance impedance impedance Note: * High level output when MOS pull-up is in on state.
Rev. 6.00 Sep 12, 2006 page 521 of 526 REJ09B0326-0600
Appendix E Product Code Lineup
Appendix E Product Code Lineup
Table E.1 Product Lineup
Product Code Mark Code Standard HD6473644H HD6473644H products HD6473644RH HD6473644P HD6473644P HD6473644RP HD6473644W HD6473644W HD6473644RW FLASH HD64F3644H HD64F3644P HD64F3644W Mask ROM version HD64F3644H HD64F3644P HD64F3644W Package (Package Code) 64-pin QFP (FP-64A) 64-pin SDIP (DP-64S) 80-pin TQFP (TFP-80C) 64-pin QFP (FP-64A) 64-pin SDIP (DP-64S) 80-pin TQFP (TFP-80C)
Product Type H8/3644 ZTATTM version
HD6433644H HD6433644(***)H 64-pin QFP (FP-64A) HD6433644RH HD6433644P HD6433644(***)P 64-pin SDIP (DP-64S) HD6433644RP HD6433644W HD6433644(***)W 80-pin TQFP (TFP-80C) HD6433644RW
H8/3643
FLASH
Standard HD64F3643H products HD64F3643P HD64F3643W
HD64F3643H HD64F3643P HD64F3643W
64-pin QFP (FP-64A) 64-pin SDIP (DP-64S) 80-pin TQFP (TFP-80C)
Mask ROM version
HD6433643H HD6433643(***)H 64-pin QFP (FP-64A) HD6433643RH HD6433643P HD6433643(***)P 64-pin SDIP (DP-64S) HD6433643RP HD6433643W HD6433643(***)W 80-pin TQFP (TFP-80C) HD6433643RW
Rev. 6.00 Sep 12, 2006 page 522 of 526 REJ09B0326-0600
Appendix E Product Code Lineup Package (Package Code) 64-pin QFP (FP-64A) 64-pin SDIP (DP-64S) 80-pin TQFP (TFP-80C)
Product Type H8/3642 FLASH
Product Code Mark Code Standard HD64F3642AH HD64F3642AH products HD64F3642AP HD64F3642AP HD64F3642AW HD64F3642AW
Mask ROM version
HD6433642H HD6433642(***)H 64-pin QFP (FP-64A) HD6433642RH HD6433642P HD6433642(***)P 64-pin SDIP (DP-64S) HD6433642RP HD6433642W HD6433642(***)W 80-pin TQFP (TFP-80C) HD6433642RW
H8/3641
Mask ROM version
Standard HD6433641H HD6433641(***)H 64-pin QFP (FP-64A) products HD6433641RH HD6433641P HD6433641(***)P 64-pin SDIP (DP-64S) HD6433641RP HD6433641W HD6433641(***)W 80-pin TQFP (TFP-80C) HD6433641RW
H8/3640
Mask ROM version
Standard HD6433640H HD6433640(***)H 64-pin QFP (FP-64A) products HD6433640RH HD6433640P HD6433640(***)P 64-pin SDIP (DP-64S) HD6433640RP HD6433640W HD6433640(***)W 80-pin TQFP (TFP-80C) HD6433640RW
Note: For mask ROM versions, (***) is the ROM code.
Rev. 6.00 Sep 12, 2006 page 523 of 526 REJ09B0326-0600
Appendix F Package Dimensions
Appendix F Package Dimensions
The package dimension that is shown in the Package Data Book has priority.
JEITA Package Code P-QFP64-14x14-0.80 RENESAS Code PRQP0064GB-A Previous Code FP-64A/FP-64AV MASS[Typ.] 1.2g
HD
*1
D 33
48
49
32 bp b1
NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
c1
*2
HE
E
c
Terminal cross section
ZE
17 64
Reference Symbol
Dimension in Millimeters
1 ZD
16 F
A1
L L1
Detail F
e
*3
y
bp
x
M
D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1
Nom Max 14 14 2.70 16.9 17.2 17.5 16.9 17.2 17.5 3.05 0.00 0.10 0.25 0.29 0.37 0.45 0.35 0.12 0.17 0.22 0.15 0 8 0.8 0.15 0.10 1.0 1.0 0.5 0.8 1.1 1.6
Min
A
A2
Figure F.1 FP-64A Package Dimensions
Rev. 6.00 Sep 12, 2006 page 524 of 526 REJ09B0326-0600
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Appendix F Package Dimensions
JEITA Package Code P-SDIP64-17x57.6-1.78 RENESAS Code PRDP0064BB-A Previous Code DP-64S/DP-64SV MASS[Typ.] 8.8g
D
64
33
1 b3 Z
32
A1
A
E
L
Reference Symbol
Dimension in Millimeters
Min
e
bp
e1
c
e1 D E A A1 bp b3 c e Z L
Nom Max 19.05 57.6 58.5 17.0 18.6 5.08
0.51 0.38 0.48 0.58 1.0 0.20 0.25 0.36 0 15 1.53 1.78 2.03 1.46 2.54
Figure F.2 DP-64S Package Dimensions
Rev. 6.00 Sep 12, 2006 page 525 of 526 REJ09B0326-0600
Appendix F Package Dimensions
JEITA Package Code P-TQFP80-12x12-0.50 RENESAS Code PTQP0080KC-A Previous Code TFP-80C/TFP-80CV MASS[Typ.] 0.4g
HD
*1
D 41
60
61
40 bp b1
NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
c1
*2
HE
E
c
Terminal cross section
80 21
Reference Symbol
Dimension in Millimeters
1 ZD Index mark
20
F
A1
L L1
e
*3
y
bp
Detail F
x M
D E A2 HD H1 A A1 bp b1 c c1 e x y ZD ZE L L1
Nom Max 12 12 1.00 13.8 14.0 14.2 13.8 14.0 14.2 1.20 0.00 0.10 0.20 0.17 0.22 0.27 0.20 0.12 0.17 0.22 0.15 0 8 0.5 0.10 0.10 1.25 1.25 0.4 0.5 0.6 1.0 Min
ZE
A2
Figure F.3 TFP-80C Package Dimensions Note: In case of inconsistencies arising within figures, dimensional drawings listed in the Package Data Book take precedence and are considered correct.
Rev. 6.00 Sep 12, 2006 page 526 of 526 REJ09B0326-0600
A
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Renesas 8-Bit Single-Chip Microcomputer Hardware Manual H8/3644 Group, H8/3644R Group, H8/3644 F-ZTATTM, H8/3643 F-ZTATTM, H8/3642A F-ZTATTM
Publication Date: 1st Edition, September 1999 Rev.6.00, September 12, 2006 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp.
(c)2006. Renesas Technology Corp., All rights reserved. Printed in Japan.
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
RENESAS SALES OFFICES
Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
http://www.renesas.com
Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510
Colophon 6.0
H8/3644 Group, H8/3644R Group, H8/3644 F-ZTATTM, H8/3643 F-ZTATTM, H8/3642A F-ZTATTM Hardware Manual

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